This paper presents the process flow optimizations for the 3D stacking of thin silicon dies. This process is developed for the postfabrication 3D integration technique, which can be used by 3D packaging and heterogenous or hybrid integration fabs. Bonding of the thin silicon layers is optimized by reducing the epoxy thickness. Further, a detailed of set experiments were used to characterize the stress in the thin silicon films. Finally, a hybrid process flow is demonstrated for achieving finer interconnect linewidths of 10 μm. The 3D stacking approach is based on the bonding of thin dies followed by SU-8 planarization. Vias are opened in the planarization layer using lithography. The interconnection methodology fills the SU-8 polymer vias with inkjet-printed silver. Printing the interconnect lines using the standard inkjet printer limits the linewidth to ∼100 μm. To address this, a hybrid process is developed to scale the interconnect line widths. Along with interconnects in the multilayer stack, we demonstrate a minimum line width and spacing of 10 μm and a via diameter of 10 μm.

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