<p>"This work has been submitted to the IEEE Transactions on Affective Computing for possible publication. Copyright may be transferred without notice, after which this version may no longer be accessible."</p><p><br></p><p>Physiological sensing has long been an indispensable fixture for virtual reality (VR) gaming studies. Moreover, VR induced stressors are increasingly being used to assess the impact of stress on an individual’s health and well-being. This study discusses the results of experimental research comprising multimodal physiological signal acquisition from 31 participants during a Go/No-Go VR-based shooting exercise where participants had to shoot the enemy and spare the friendly targets. The study encompasses multiple sessions, including orientation, thresholding, and shooting. The shooting sessions consist of tasks under low & high difficulty induced stress conditions with in-between baseline segments. Machine learning (ML) performance with heart rate variability (HRV) from electrocardiogram (ECG) and electroencephalogram (EEG) features outperform the prevalent methods for four different VR gaming difficulty-induced stress (GDIS) classification problems (CPs). Further, the significance of the HRV predictors and different brain region activations from EEG is deciphered using statistical hypothesis testing (SHT). The ablation study shows the efficacy of multimodal physiological sensing for different gaming difficulty-induced stress classification problems (GDISCPs) in a VR shooting task.</p>

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This paper describes the design optimization and analysis of the digital hardware of a high-speed direct digital frequency synthesizer (DDFS) implemented using the NanGate 45nm Open Cell library. The digital blocks of the DDFS generate 13-bit accurate sinusoidal waveform in the frequency range of 0 − 500 MHz. The DDFS uses a 1.5 GHz input clock, a ROM-less phase to amplitude converter (PAC) based on the CORDIC algorithm, and has a frequency tuning resolution of 1 mHz. Fixed-point simulations and analysis were performed to obtain the finite hardware bit-widths to meet the desired Signalto-Noise-Ratio (SNR) and Spurious-Free Dynamic Range (SFDR) performance. Multiple quantization schemes were compared and the optimum scheme, which meets the hardware timing constraints and the desired system performance, is selected for the final hardware implementation.

<p>This work has been submitted to the IEEE for possible publication. Copyright may be transferred without notice, after which this version may no longer be accessible. </p>

<p>This work has been submitted to the IEEE for possible publication. Copyright may be transferred without notice, after which this version may no longer be accessible. </p>