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This paper presents a frequency compensation scheme of a full GaN operational amplifier for smart power applications. The amplifier is based on a previous topology originally developed for nMOS technology and here adapted for a modern GaN process. The solution is able to drive a capacitive load as high as 1 nF and a suitable design strategy has been developed. The operational amplifier exhibits a very high nominal DC gain of about 135 dB, a unity-gain bandwidth of about 560 kHz with 60°phase margin, a slew rate of about 0.83 V/µs and a nominal quiescent current consumption of 200 µA from a 6-V supply.

This paper presents a gate driver topology designed in a GaN on Si technology to be implemented on the same substrate with a 650-V, 500-mΩ power GaN switch. The driver consists of three buffer stages, three anti-cross conduction networks, two level shifters, and three bootstrap capacitors. Simulations of the proposed GaN driver are presented and a comparison with the conventional solution, assuming the same static current consumption, is provided. The proposed circuit not only solves cross-conduction problems, which are crucial for the limitation of undue dynamic power consumption, but it is also aimed at limiting static current consumption by using a bootstrap technique. Simulations show that the power GaN transistor driven by a 6-V, 2.5-MHz PWM signal with 50% duty cycle through the proposed driver, reaches a nominal switching speed as high as 50 V/ns at 27 °C, with an average current consumption of about 1 mA, over the entire range of temperature from −40 °C to 150 °C.

This paper presents an integrated soft start-upcircuit implemented in a 0.5-μm GaN on Si technology suitable for on-chip integration in power applications. The proposed approach avoids the use of large on-chip or external capacitors to overcome the problem of voltage overshoot and inrush current at start up in switching power converters. It could be also adapted to the specific application by choosing the number of Flip Flops, or, for large start-up periods, using a counter, and setting the desired start-up signal duty cycle. Moreover, an optimized Flip Flop circuit topology has been proposed to reduce area occupation.The circuit working principle and the design challenges in GaN technology are discussed together with simulations. The circuit has been designed by considering worst-case conditions. A test buffer has been also included to drive the high external load capacitance of the readout device. Measured waveforms are reported that demonstrate the effective circuit operation and suitability for all-GaN integration.

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