Etch performances of inductory-coupled plasma (ICP) metal etchers with several gas systems are examined under constant ion energy condition to evaluate extendibility to the 300 mm wafer magnetic tunnel junction (MTJ) etch process. The ICP-Ar sputter etch affects little on magnetic properties, and shows about the same magnetoresistive (MR) ratio with conventional Ar ion milling. Major issue is the electrical short by redeposition. The etch uniformity over the wafer and precise etch end-point detection are important. The Cl2 addition to the ICP-Ar etch plasma shows serious pattern deformation and degradation of loop offset (H off). Methanol (Me-OH) etch shows slightly lower MR-ratio due to material degradation. However, better H off is observed probably due to the ion protection effect by thin carbon layer over the etched surface. Dilution of Me-OH with Ar improves MR ratio. Ar/Me-OH and ICP-Ar etch processes would be the candidate for 300 mm process at present.

Thickness dependence of current-induced domain wall (DW) motion in a perpendicularly magnetized [Co/Ni]N multilayered wire containing Ta/Pt capping and Pt/Ta seed layers has been studied. The thickness of the magnetic layer was controlled by the stacking number, N. The threshold current density for driving DW had a local minimum at N = 3 and the velocity of DW motion decreased with N. Estimation of carrier spin polarization from measurements of DW velocity revealed that a thinner Co/Ni stack adjacent to the Pt layers reduced the carrier spin polarization and the strength of adiabatic spin transfer torque.

This paper describes experimental results obtained from measuring the dependence of device temperature on the current for domain wall motion in a Co/Ni wire having perpendicular magnetic anisotropy. Devices with different insulating layer thicknesses were prepared in order to control the device temperature. A stable domain wall motion was observed up to the temperature at which perpendicular magnetic anisotropy vanishes. Moreover, the current required for domain wall motion was independent of the device temperature.

We proposed a new statistic w spectrum which can detect the shot width distribution sensitively. By applying the w spectrum to X-ray binaries, we can distinguish between neutron stars and black holes from their different shot behaviours at small timescales. The energy dependent analysis for black hole binaries, in particular for Cyg X-1, can help us to reveal dynamical evidence for black hole accretion flows and state transitions. Both narrow and broad iron Kα lines are presented in the w analysis, affording dynamical evidence for iron lines origin.

Since MRAM cells have unlimited write endurance, they can be used as substitutes for DRAMs or SRAMs. MRAMs in electronic appliances enhance their convenience and energy efficiency because data in MRAMs are nonvolatile and retained even in the power-off state. Therefore, 2 to 16Mb standalone MRAMs have been developed [1][2][3][4]. However, in terms of their random-access times, they are not enough fast (25ns) [1] as substitutes for all kinds of standalone DRAMs or SRAMs. To attain a standalone MRAM with both a fast random-access time and a large capacity, we adopt a cell structure with 2 transistors and 1 magnetic tunneling junction (2T1MTJ), which we previously published for a 1Mb embedded MRAM macro [5]. We need to develop circuit schemes to achieve a larger memory capacity and a higher cell-occupation ratio with small access-time degradation. We describe the circuit schemes of a 32Mb MRAM, which enable 63% cell occupation ratio and 12ns access time. Figure 27.4.1 shows a block diagram of 32Mb MRAM.The interface is compatible with asynchronous high-speed SRAMs. Our developed 32Mb MRAM includes four synchronous 10Mb macros (MMACs) and peripheral circuits. Each MMAC includes ten 1Mb sub macros (SMACs). One of the peripheral circuits is an asynchronous-to-synchronous convertor and an ECC encoder/decoder using a (32 + 8) bit Reed-Solomon code, which effectively corrects multiple errors. An internal power-supply circuit supplies a 1V core voltage (V DD ) and 1.5V boosted voltage (V DH ). Each SMAC includes four sets of redundant columns and two sets of redundant rows.To achieve an increase of memory capacity, reduction of cell area is essential. The 2T1MTJ cell area is proportional to the writing current for switching the magnetization of the magnetic storage layer. To reduce cell area, we have been reducing the switching current of the magnetic storage layer [6]. As another scheme for cell area reduction, we use boosted a wordline technique in the 32Mb MRAM design. The selected wordline is driven by a voltage V DH , which is higher than V DD . A 1.5V VDH improves drivability of cell transistors, and the gate width of cell transistors is reduced by half, as shown in Fig. 27.4.2. We achieve a memory cell area of 0.66×2.08µm 2 with a 1mA conducting current. The area is comparable to that of a 6T SRAM in the same process technology.However, the use of a boosted wordline technique causes access-time degradation because boosted wordline drivers are complicated compared to normal ones. To diminish the degradation, we use a specific type of the wordline driver with an additional power supply, as shown in Fig. 27.4.3. Standalone memories are permitted to use an additional power supply because internal power-supply circuits are shared by many memory cell arrays. Since the voltage of a wordline, V DH , is higher than V DD , the wordline driver requires a level converter. In standby mode, the row precharge signal (RP) is at the low level and node one, N1, is precharged to the V DH . After addresses are determined, RP is at V DH...