The reduction in the transistor and interconnect dimensions have a severe impact on the reliable performance of the Field Programmable Gate Array (FPGA) circuits. The process variation effects in nanometer scale technologies result in transient errors or permanent failures that cause undesired behavior of the circuit. In this work, we analyze a method for fault identification to mitigate the impact of lifetime failures such as Electro-migration (EM) and Hot Carrier Effect (HCE) in interconnect of the FPGA. This method is based on the signal delays in routing resources that include switch blocks and interconnect wires.

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