In this paper, we review recent advances in the development of flexible thermoelectric materials and devices for wearable human body-heat energy harvesting applications. We identify various emerging applications such as specialized medical sensors where wearable thermoelectric generators can have advantages over other energy sources. To meet the performance requirements for these applications, we provide detailed design guides regarding the material properties, device dimensions, and gap fillers by performing realistic device simulations with important parasitic losses taken into account. For this, we review recently emerging flexible thermoelectric materials suited for wearable applications, such as polymer-based materials and screen-printed paste-type inorganic materials. A few examples among these materials are selected for thermoelectric device simulations in order to find optimal design parameters for wearable applications. Finally we discuss the feasibility of scalable and cost-effective manufacturing of thermoelectric energy harvesting devices with desired dimensions. 1

The implementation of a first-generation CELL processor that supports multiple operating systems including Linux consists of a 64b power processor element (PPE) and its L2 cache, multiple synergistic processor elements (SPE) [1] that each has its own local memory (LS) [2], a high-bandwidth internal element interconnect bus (EIB), two configurable non-coherent I/O interfaces, a memory interface controller (MIC), and a pervasive unit that supports extensive test, monitoring, and debug functions. The high level chip diagram is shown in Fig. 10.2.1. The key attributes include hardware content protection, virtualization and realtime support combined with extensive single-precision floatingpoint capability. By extending the Power architecture with SPE having coherent DMA access to system storage and with multioperating-system resource-management, CELL supports concurrent real-time and conventional computing. With a dual-threaded PPE and 8 SPEs this implementation is capable of handling 10 simultaneous threads and over 128 outstanding memory requests. Figure 10.2.7 shows the die micrograph with roughly 234M transistors from 17 physical entities and 580k repeaters and 1.4M nets implemented in 90nm SOI technology with 8 levels of copper interconnects and one local interconnect layer. At the center of the chip is the EIB composed of four 128b data rings plus a 64b tag operated at half the processor clock rate. The wires are arranged in groups of four, interleaved with GND and VDD shields twisted at the center to reduce coupling noise on the two unshielded wires. To ensure signal integrity, over 50% of global nets are engineered with 32k repeaters. The SoC uses 2965 C4s with four regions of different row-column pitches attached to a low-cost organic package. This structure supports 15 separate power domains on the chip, many of which overlap physically on the die. The processor element design, power and clock grids, global routing, and chip assembly support a modular design in a building-block-like construction.The chip contains 3 distinct clock-distribution systems, each sourced by an independent PLL, to support processor, bus interface, and memory-interface requirements. The main high-frequency clock grid covers over 85% of the chip, delivering the clock signal to processors and miscellaneous circuits. Second and third clock grids, each operating at fractions of the main clock signal, are interleaved with the main clock-grid structure, creating multiple clock frequency islands within the chip. All clock grids are constructed on the lowest impedance final two layers of metal, and are supported by a matrix of over 850 individually tuned buffers. This enables control of the clock-arrival times and skews, especially on the main clock grid that supports regions of widely varying clock-load densities. High-frequency clock-signal distribution optimization and verification rely on wire simulation models that includes frequency-sensitive inductance and resistance phenomena. As shown in Fig. 10.2.2, final worst-case clock skew ac...

The energy conversion efficiency of today's thermoelectric generators is significantly lower than that of conventional mechanical engines. Almost all of the existing research is focused on materials to improve the conversion efficiency. Here we propose a general framework to study the cost-efficiency trade-off for thermoelectric power generation. A key factor is the optimization of thermoelectric modules together with their heat source and heat sinks. Full electrical and thermal co-optimization yield a simple analytical expression for optimum design. Based on this model, power output per unit mass can be maximized. We show that the fractional area coverage of thermoelectric elements in a module could play a significant role in reducing the cost of power generation systems.