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Approach to full-chip simulation and correction of stencil mask distortion for proximity electron lithographyWe have devised a new mask format for low-energy electron-beam proximity-projection lithography ͑LEEPL͒ that enables faster and more accurate image transfer from the mask to a wafer, in comparison with the single-membrane mask as originally proposed. Simultaneous exposure over four adjacent complementary quadrants of the mask, synchronized with step-and-repeat motion of the wafer stage, yields one complete pattern with the throughput of ϳ30 wafers/h. Mechanical analysis has demonstrated that the new format also offers better controllability of image placement owing to smaller membranes, even though the gravitational deformation of the mask, for example, must still be corrected for.

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a)Sony, Kapeldreef 75, Leuven, Belgium B-3001 (b)imec, Kapeldreef 75, Leuven, Belgium B-3001 (c)ASML Brion, ABSTRACTSource mask optimization (SMO) and double patterning technology (DPT) are considered key Resolution Enhancement Technique (RET) enablers for scaling 2x nodes and beyond design rules, using existing 193 nm ArF technology prior to EUV availability. SMO has been extensively shown to enlarge the process margin for critical layers in memory cells and test patterns; however the best SMO flow for a large random logic area up to full-chip application has been less explored. In this study, we investigated how the mask complexity in the source optimization impacts the final process window on a random logic layout after DPT, and proposed a new source optimization approach. Example used is a contact layer for 2x logic designs. The SMO source optimization is performed using the SRAM cells with different mask complexities. These optimized sources are then evaluated based on a large-area random logic layout after mask-only optimization. CD variation through process window is used as the metric for comparison. We found the best result is obtained when the source is optimized with the full flexibility of the source and mask with freeform SRAFs and minimal MRC constraints. The source optimized with this approach can reduce CD variation through process window in the random logic without increasing its mask complexity.