On-site use of 1x stencil mask: control over image placement and dimension

Omori, Shinji; Iwase, Kazuya; Watanabe, Yoko; Amai, Keiko; Sasaki, Takayuki; Nohama, Shoji; Ashida, Isao; Moriya, Shinji; Kitagawa, Tetsuya

doi:10.1117/12.504258

Cited by 5 publications

(5 citation statements)

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“…Indeed, the IP error for EB writing has been evaluated and is less than 20 nm. 7 The variation of the mask flatness between the EB writer and the LEEPL tool can induce large IP errors because the warp of the mask is a few tenth µm if an SOI wafer is used. This error can be suppressed via both the use of a flat SOI substrate and the consistent chucking methods over the different equipments.…”

Section: Overlaymentioning

confidence: 99%

“…On the other hand, the 200-mm mask without a frame that is fully compatible with the mask fabrication infrastructures for electron-beam projection lithography (EPL) 6 is used for the production tool. 7 There are two straightforward concerns, however, with regard to the use of a 1x stencil mask. Firstly, the control of IP and CD on the mask level is a challenge.…”

Section: Introductionmentioning

confidence: 99%

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Litho-and-mask concurrent approach to the critical issues for proximity electron lithography

et al. 2003

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The performance of the LEEPL production tool is discussed from the framework of the litho-and-mask concurrent development schemes to establish the feasibility of proximity electron lithography (PEL) especially for contact and via layers in the 65-nm technology node. The critical-dimension (CD) uniformity of 4.7 nm has been achieved for 90-nm contact holes over the 1x stencil mask. Thus, the mask patterns can be transferred onto the resist layer with CD errors of less than 10%, even if the mask-error enhancement factor (MEEF) of 1.6 is taken into account. The mask manufacturability is improved if the MEEF further decreases via the use of thinner resists. Meanwhile, the overlay accuracy of 21.1 nm has been achieved in mix-and-match with the ArF scanner, with the intra-field error of only 5.1 nm owing to the real-time correction for the mask distortion. Also, the conditions for splitting dense lines into two complementary portions have been determined to avoid the pattern collapse in wet-cleaning and drying processes. The critical length of 2 µm is fairly safe for 70-nm lines if the low-damage drying is employed. The inspection tool based on transmission electron images cannot detect all printable defects without further optimization, hence a future challenge.

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Section: Overlaymentioning

confidence: 99%

Section: Introductionmentioning

confidence: 99%

Litho-and-mask concurrent approach to the critical issues for proximity electron lithography

et al. 2003

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“…4 So we chose 200-mm without frame type format for production mask. From a point of view for dust control, the format with frame isn't preferable, too.…”

Section: Mask Formatmentioning

confidence: 99%

LEEPL mask fabrication using SOI substrates

2003

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We have prepared 100-mm and 200-mm 1X stencil masks for low energy electron-beam proximity projection lithography (LEEPL) using silicon on insulator (SOI) substrates. We chose 200-mm without frame type format for production mask and 100-mm with NIST-like frame type for developing. And we employed COSMOS (complementary stencil masks on strut-supports) structure proposed by SONY to suppress in-plane distortion (IPD) of membrane. Our 100-mm mask contains 70-nm node device patterns. The critical dimension (CD) uniformity of a 100-nm width line patterns was 5.6 nm in range within 20-mm square area. The CD linearity of the line patterns was 5.5 nm in range throughout the range of 80-to 300-nm width. In our 200-mm mask, 100-nm width line patterns and 150-nm width hole patterns were successfully fabricated within 46-mm square area.

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“…2, the proposed image-placement (IP) correction method is revisited briefly, and then the experimental setups are explained in Sec. 3. In Sec.…”

Section: Introductionmentioning

confidence: 96%

“…In this paper, thus, a more production-compatible method, conceptually proposed earlier, 3 is demonstrated, where the image placement (IP) error over a 1x stencil mask, chucked onto a newly developed holder, are gauged at a mask shop using the metrology tool LMS IPRO (Laica) and fed forward to the exposure tool for real-time IP correction at a wafer FAB. In Sec.…”

Section: Introductionmentioning

confidence: 99%

Feedforward correction of mask image placement for proximity electron lithography

et al. 2004

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A production-compatible method for the correction of image-placement (IP) error over a 1x stencil mask as used for proximity electron lithography (PEL) has been demonstrated. The mask IP error as measured using a newly developed metrology tool was fed forward to the PEL stepper, LEEPL-3000 and corrected for via the fine deflection of the electron beam. The overlay errors with respect to the substrate patterned by the ArF scanner have decreased from 63.6/59.3 nm to 26.1/36.4 nm in the x/y directions, but they are still larger than the errors of 15.2/14.8 nm for the conventional feedback method. Therefore, some improvements in the metrology method, the mask chucking method, the mask flatness and so on are required.

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On-site use of 1x stencil mask: control over image placement and dimension

Cited by 5 publications

References 0 publications

Litho-and-mask concurrent approach to the critical issues for proximity electron lithography

Litho-and-mask concurrent approach to the critical issues for proximity electron lithography

LEEPL mask fabrication using SOI substrates

Feedforward correction of mask image placement for proximity electron lithography

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