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A production-compatible method for the correction of image-placement (IP) error over a 1x stencil mask as used for proximity electron lithography (PEL) has been demonstrated. The mask IP error as measured using a newly developed metrology tool was fed forward to the PEL stepper, LEEPL-3000 and corrected for via the fine deflection of the electron beam. The overlay errors with respect to the substrate patterned by the ArF scanner have decreased from 63.6/59.3 nm to 26.1/36.4 nm in the x/y directions, but they are still larger than the errors of 15.2/14.8 nm for the conventional feedback method. Therefore, some improvements in the metrology method, the mask chucking method, the mask flatness and so on are required.

Proximity electron lithography (PEL) using the ultra-thin tri-layer resist system has been successfully integrated in our dual-damascene Cu/low-k interconnects technology for the 90-nm node. Critical comparison between conventional ArF lithography and PEL as to the via-chain yield for test element groups (TEGs) including approximately 2.9 million via chains was performed to demonstrate its production feasibility.

Imaging capabilities of low-energy electron-beam proximity-projection lithography (LEEPL) are discussed focusing mainly on the hole patterns for chemically amplified resist. LEEPL needs a multi-layer process with a resist layer less than 100 nm thick. To achieve the imaging performance of the 65nm node (80nm), we optimized intermediate spin-on-glass (SOG) layer and top-layer resists, which were selected carefully. 80 nm hole patterns were achieved with 10% exposure latitude, and current imaging position and 45 nm node positions were investigated using σ QBP. σ QBP was improved from 64.5 nm to 48.9 nm.

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