BEOL process technology based on proximity electron lithography: demonstration of the via-chain yield comparable with ArF lithography

Nohdo, Shinichiro; Omori, Shinji; Iwase, Kazuya; Yoshizawa, Masaki; Motohashi, Tomonori; Oguni, Kumiko; Nakayama, Keiichi I.; Egawa, H.; Takeda, T.; Morikawa, Takeshi; Nohama, Shoji; Nakano, Hiroyuki; Kitagawa, Tetuya; Moriya, Shinji; Kawahira, Hiroichi

doi:10.1117/12.601733

Cited by 3 publications

(2 citation statements)

References 10 publications

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“…To control pattern collapse, Koba et al [2] indicated and demonstrated that tri-layer resist process had a high applicability for device fabrication in BEOL. Nohdo et al [3] also indicated Proximity electron lithography (PEL) using the ultra-thin tri-layer resist system has been successfully integrated in our dual-damascene Cu/low-k interconnects technology for the 90-nm process. Matsuura et al [4] describes process optimisation of UV curing for ultra Low-k SiOC (ULK-SiOC, k = 2.65) and High stress silicon nitride (HS-SiN) liner.…”

Section: Introductionmentioning

confidence: 99%

Novel Approach of Semiconductor Manufacturing Process on Copper Dual Damascene Processes Integration

Weng

2009

Strain

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The performance of the manufacturing process in each of these areas determines the overall manufacturability of the process. As device geometries are reduced, understanding and minimising the sources of process-induced defects is critical to achieving and maintaining high device yields. This paper presents a comprehensive investigation of a novel metrology on semiconductor process module integration and technology on optimal integrated lithography processes and solution to the problem of defects reduction on semiconductor wafer in sub-micron processes integration. As dual damascene integration copper process is complicated and critical in semiconductor processes. It has been common knowledge that pattern collapse and missing of this process and numerous defects could be prevented by optimal the process module tuning. To investigate novel semiconductor process integration on deep pattern aspect ratio effects of sub-micron semiconductor wafer BEOL (Back-End-Of-Line) structure were included in this study. Moreover, the electrical device investigations of device checking were also included.

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Section: Introductionmentioning

confidence: 99%

Novel Approach of Semiconductor Manufacturing Process on Copper Dual Damascene Processes Integration

Weng

2009

Strain

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“…To control pattern collapse, Koba et al 2) proposed and demonstrated that a trilayer resist process has high applicability in device fabrication. Nohdo et al 3) also demonstrated proximity electron lithography (PEL) using an ultrathin trilayer resist system, which has been success-fully integrated into a dual-damascene Cu/low-k interconnect technology for the 90 nm process. Matsuura et al 4) described the process optimization of curing for ultralow-k SiOC (k ¼ 2:65) and a high-stress silicon nitride (HS-SiN) liner.…”

Section: Introductionmentioning

confidence: 99%

Optimal Integration Process for Elimination of Abnormal Striation on Wafer Dual Damascene Processes

Weng¹

2009

jjap

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This paper is focused on optimal lithography processes using copper back-end-of-line (BEOL) semiconductor wafer integration technology and a solution to the problem of defect reduction on a semiconductor wafer. The pattern collapse observed in this process and numerous defects were prevented by optimizing the process module tuning. A novel semiconductor process on various pattern designs and deep pattern aspect ratio effects of a submicron semiconductor structure were included in this study. In addition to the experimental wafer manufacturing process, the electrical device data and defect reduction checking were also included.

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A Novel Sub-Micron Semiconductor Gap Fill Integrated Processes

Weng¹

2007

2007 IEEE Conference on Electron Devices and Solid-State Circuits

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BEOL process technology based on proximity electron lithography: demonstration of the via-chain yield comparable with ArF lithography

Cited by 3 publications

References 10 publications

Novel Approach of Semiconductor Manufacturing Process on Copper Dual Damascene Processes Integration

Novel Approach of Semiconductor Manufacturing Process on Copper Dual Damascene Processes Integration

Optimal Integration Process for Elimination of Abnormal Striation on Wafer Dual Damascene Processes

A Novel Sub-Micron Semiconductor Gap Fill Integrated Processes

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