Alignment accuracy of LEEPL: image placement error correction

Nohdo, Shinichiro; Motohashi, Tomonori; Shimazu, Nobuo; Nakano, Hiroyuki; Omori, Shinji; Kitagawa, Tetsuya; Moriya, Shinji

doi:10.1117/12.504067

Cited by 4 publications

(4 citation statements)

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“…The results are summarized in Table 2, together with the results for the β-tool. 4 Even though the dynamic stability should be assessed, the TOL error is compatible with the requirement for the 65-nm node. …”

Section: Overlaymentioning

confidence: 97%

“…The image-placement (IP) error over the mask can be corrected for by slightly tilting the direction of the EB using the sub-deflectors with the applied voltages varying according to the pre-determined database. 4 At present, the β-and production tools are available to us for evaluating their performances (the β2-tool is also open to applicants). The β-tool has been designed exclusively for 200-mm wafers, while the production tool (LEEPL-3000) can accommodate both 200-mm and 300-mm wafers.…”

Section: Introductionmentioning

confidence: 99%

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Litho-and-mask concurrent approach to the critical issues for proximity electron lithography

et al. 2003

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The performance of the LEEPL production tool is discussed from the framework of the litho-and-mask concurrent development schemes to establish the feasibility of proximity electron lithography (PEL) especially for contact and via layers in the 65-nm technology node. The critical-dimension (CD) uniformity of 4.7 nm has been achieved for 90-nm contact holes over the 1x stencil mask. Thus, the mask patterns can be transferred onto the resist layer with CD errors of less than 10%, even if the mask-error enhancement factor (MEEF) of 1.6 is taken into account. The mask manufacturability is improved if the MEEF further decreases via the use of thinner resists. Meanwhile, the overlay accuracy of 21.1 nm has been achieved in mix-and-match with the ArF scanner, with the intra-field error of only 5.1 nm owing to the real-time correction for the mask distortion. Also, the conditions for splitting dense lines into two complementary portions have been determined to avoid the pattern collapse in wet-cleaning and drying processes. The critical length of 2 µm is fairly safe for 70-nm lines if the low-damage drying is employed. The inspection tool based on transmission electron images cannot detect all printable defects without further optimization, hence a future challenge.

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Section: Overlaymentioning

confidence: 97%

Section: Introductionmentioning

confidence: 99%

Litho-and-mask concurrent approach to the critical issues for proximity electron lithography

et al. 2003

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“…13 In this work, overlay marks were located within the shot area, and the correction table was made on the basis of the metrological results for exposed wafers. The achieved total overlay errors were 21.4/21.5 nm in the x and y directions, respectively in mean plus 3σ in the vicinity of the via-chain TEGs.…”

Section: Alignmentmentioning

confidence: 99%

BEOL process technology based on proximity electron lithography: demonstration of the via-chain yield comparable with ArF lithography

et al. 2005

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Proximity electron lithography (PEL) using the ultra-thin tri-layer resist system has been successfully integrated in our dual-damascene Cu/low-k interconnects technology for the 90-nm node. Critical comparison between conventional ArF lithography and PEL as to the via-chain yield for test element groups (TEGs) including approximately 2.9 million via chains was performed to demonstrate its production feasibility.

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“…In particular, the intra-field error has been suppressed at 10.2 nm by using the fine deflectors that can vary the direction of an electron beam (EB) according to the pre-determined intra-field distortion. 2 However, collecting the distortion data requires "pilot" exposure and overlay metrology measurement prior to device production. Also, placement of marks for overlay metrology is limited only in the so-called scribe lines around device regions, so that the accurate sampling of the intra-field distortion is not always possible.…”

Section: Introductionmentioning

confidence: 99%

Feedforward correction of mask image placement for proximity electron lithography

et al. 2004

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A production-compatible method for the correction of image-placement (IP) error over a 1x stencil mask as used for proximity electron lithography (PEL) has been demonstrated. The mask IP error as measured using a newly developed metrology tool was fed forward to the PEL stepper, LEEPL-3000 and corrected for via the fine deflection of the electron beam. The overlay errors with respect to the substrate patterned by the ArF scanner have decreased from 63.6/59.3 nm to 26.1/36.4 nm in the x/y directions, but they are still larger than the errors of 15.2/14.8 nm for the conventional feedback method. Therefore, some improvements in the metrology method, the mask chucking method, the mask flatness and so on are required.

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Alignment accuracy of LEEPL: image placement error correction

Cited by 4 publications

References 0 publications

Litho-and-mask concurrent approach to the critical issues for proximity electron lithography

Litho-and-mask concurrent approach to the critical issues for proximity electron lithography

BEOL process technology based on proximity electron lithography: demonstration of the via-chain yield comparable with ArF lithography

Feedforward correction of mask image placement for proximity electron lithography

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