In this paper, a new data reading technique for a bus of lines is proposed for fast operation. The proposed method utilizes multiple reference voltages available within a line's receiving logic and the initial conditions of wires in order to determine early and accurately the transmitted data of the current cycle. The presented technique does not require repeater insertion for reasonably long lines and it can significantly accelerate signal propagation. Experimental results are given in the 65 nm CMOS process for interconnects of various lengths.

Coupling and increasing wire resistance on interconnect fabrics undermine the speed of the transient electrical signals. A brute-force approach for a crosstalk-reduced design relies on increasing the distance of interconnects from each other and using additional repeated logic. A pipelined bus-architecture exploiting the existing electrical noise is proposed. Process variations are taken into consideration in the analysis. The proposed technique is validated for the 65nm and 90nm CMOS processes for interconnects of various lengths.9th International Symposium on Quality Electronic Design 0-7695-3117-2/08 $25.00

No abstract