No abstract

Optoelectronic imaging of integrated-circuits has revolutionized device design debug, failure analysis and electrical fault isolation; however modern probing techniques like laser-assisted device alteration (LADA) have failed to keep pace with the semiconductor industry's aggressive device scaling, meaning that previously satisfactory techniques no longer exhibit a sufficient ability to localize electrical faults, instead casting suspicion upon dozens of potential root-cause transistors. Here, we introduce a new high-resolution probing technique, two-photon laser-assisted device alteration (2pLADA), which exploits two-photon absorption (TPA) to provide precise three-dimensional localization of the photo-carriers injected by the TPA process, enabling us to implicate individual transistors separated by 100 nm. Furthermore, we illustrate the technique's capability to reveal speed-limiting transistor switching evolution with an unprecedented timing resolution approaching <10 ps. Together, the exceptional spatial and temporal resolutions demonstrated here now make it possible to extend optical fault localization to sub-14 nm technology nodes.

In order to enhance the utility of pulsed laser deposition, a method to deposit uniform films has been devised. The target and substrate are offset from each other and the substrate is rotated about its axis between laser pulses. We have simulated this process using experimentally determined deposition profiles. Films of uniform thickness to within a few percent across a substrate 5.08 cm in diameter have been fabricated, where we have obtained excellent agreement between theory and experiment.

In this paper, we describe improved hardware to connect a semiconductor tester or applications board to a laser scanning microscope (LSM) for performing dynamic laser stimulation (DLS). The hardware, called DXGlue, simplifies the DLS workflow and enables new applications. We describe its precise monitoring of the fail rate and fail mode, its use for time resolved DLS and the enabling of long test loops with short laser dwell times.

The struggle against positive mobile ionic contamination (PMIC) in integrated circuit devices continues in spite of the tremendous gains in the purity of Semiconductor Grade starting materials. As device geometries have decreased and levels of integration have increased, package types have multiplied. Highly sophisticated analytical techniques are required to unambiguously identify the specific ions causing a particular single transistor to fail. The monitoring of VLSI wafer manufacturing and packaging process steps to assure minimal residual positive ionic contaminants takes greater efforts as the level of device-killing contaimination decreases. This tutorial presented analytical case studies for the unambiguous identification of failure-causing metal ionic contamination.The impact of PMIC on MOS devices and circuits was also discussed. The problems caused by the collection of PMIC near active devices include negative VT shifts in active and parasitic NMOSFET devices as well as increased leakage in PMOS devices. The effect of lowering the VT of an NMOS transistor results in an increased off state leakage current.In circuits the instabilities associated with PMIC are typically found after static lifetest and burn-in stresses performed at elevated temperatures. The circuits which are most susceptible to PMIC failures are those which have small restoring currents. SRAM circuits fabricated using a 4T NMOS cell with polysilicon load resistors, of approximately 10 GigaOhms to 1 TeraOhm are susceptible to this failure mechanism. Electrical failure analysis on devices with PMIC typically consists of bit mapping and microprobing failing arrays on devices before and after bake recovery. A case study of an SRAM failure analysis was given which showed the shifts of NMOS device characteristics at several measurement points during a bake recovery experiment. The results of this study show that the active NMOS transistors had shifted VT's which caused leakage currents from the SRAM storage node. Another SRAM case study was presented which characterized a bake recoverable failure mechanism which was not due to PMIC contamination, but was caused by polysilicon stringers. This last case study was given to show that bake recoverable failure mechanisms are not always due to IPMIC. complex multilayer imetalization (MLM) are increasingly susceptible to positive mobile ion contamination. A nondestructive, low cost electrical method for monitoring PMIC in MLlM structures is very desirable. Electrical measurements of mobile ion contamination in integrated circuit processing are typiciilly performed on a MOS capacitor using CV bias-temperature stressing or the triangular voltage sweep (TVS) technique. An advantage of TVS is that it does not specifically require a MOS capacitor. This allows the TVS method to be extendled to multilevel metalization structures. Advanced CMOS and BiCMOS technologies withThe capacity atf TVS for measuring mobile ions in a variety of practical MLM structures including metal-1 edge intensive, metal-2 edge inte...