Implications of fundamental threshold voltage variations for high-density SRAM and logic circuits

Suppression of random dopant-induced threshold voltage fluctuations in sub-0.1-μm MOSFET's with epitaxial and δ-doped channels

“…At the same time, the integrated circuits are becoming more sensitive to the fluctuation in the MOSFET characteristics due to the reduction in the supply voltage to reduce the power consumption and to sustain the reliability. The intrinsic parameter variations and the corresponding transistor mismatch start to impinge on the performance and functionality of analog [8] and logical [17] circuits and SRAM's [18]. A relatively easy way to reduce the intrinsic parameter fluctuations, without a major change in the MOSFET architecture, is the appropriate tailoring of the channel doping profile.…”

Design And Implementation of 8T SRAM cell for Analysis of DC Noise Margin during Write Operation

“…Random variations are caused by random uncertainties in the fabrication process such as microscopic fluctuations in the number and locations of dopant atoms in the channel region [3][4]. Random variations are harder to characterize and cause a significant mismatch in neighbouring devices and hence are largely responsible for the poor yield of the static random access memory (SRAM) arrays in scaled technologies [5][6]. Moreover, SRAM cells are traditionally designed to ensure that the contents of the cell do not get altered during read access while the cell should be able to quickly change its state during the write operation.…”

Cache architectures based on heterogeneous technologies to deal with manufacturing errors

“…Among them, the random placement of dopants causes threshold voltage mismatches among transistors that are spatially close to each other. Because of the small geometry of the SRAM cell, the main source of the device mismatch is the intrinsic fluctuation of the Vth of different transistors due to random dopant fluctuations [6,8,15], that is, random intra-die variations. These device parameters mismatches severely affect SRAM cells in sub-50nm technologies [1].…”