No abstract

The delay dependency of digital circuits on process, voltage and temperature variations are usually compensated by using safety margins that set the limit of operating supply voltage or clock frequency. Razor enables the processor to operate beyond this safety margin through the utilization of error detection and recovery circuits. In this paper, a single chip dual ARM9 core solution, with and without Razor, is implemented in 65nm CMOS to accurately characterize the added resiliency introduced by Razor. Functionality testing on the same operating environment allows for a fair characterization by isolating delay dependencies caused by PVT variations.