The desired specifications of the design are given in the Table I below.Generic block diagram of simple two-stage op amp is shown in figure 1 below. First stage consists of high-gain differential amplifier. Mostly cascading is used to enhance the gain in this stage. This stage has the most dominant pole of the system. A common source single stage amplifier is usually used as a second stage, which gives high output voltage swing. Third stage is most commonly implemented as the unity-gain source follower circuit [51. A. Topology SelectionFor high speed and high accuracy circuits, op amps with high open-loop DC gain, large output voltage swing, and high unity-gain bandwidth are required. Our target is to design an amplifier with 5 MHz unity-gain bandwidth, and a DC gain higher than 73 dB, with a 10 pF load. Topology that will surely satisfy this magnitude of DC gain is two-stage topology. Hence two-stage topology is chosen. Fig. 1. Block diagram of basic op amp [51 V out Output Buffer Single Stage Amplifier DESIRED SPECIFICATIONS OF THE DESIGNTABLE I. Differential -Amplifier I. INTRODUCTIONOperational amplifier is most versatile and fundamental building block in analog signal processing applications. The operational amplifier (Op Amp) is a high gain, DC coupled voltage amplifier with a differential input and, single or differential output to be used with negative feedback to precisely define a closed loop transfer function. The basic requirements for an op amp are sufficiently large open loop gain, large unity gain bandwidth, high input impedance, low output impedance, and high speed. These amplifiers are key elements of most of the analog subsystems, particularly in switched capacitor filters. For last few decades a CMOS implementation of analog circuits proved better than its counterparts as the same technology can be used to implement analog as well as digital building blocks on the same chip. This paper is focused on the design of two-stage unbuffered operational amplifier for use within single chip mixedsignal system. In section II, the design methodology for twostage CMOS op amp is addressed. In section III, achieved simulation results are presented. Finally, the outcomes of the design are concluded in section IV.Abstract-This paper presents the design of two-stage operational amplifier (Op Amp). The circuit was designed in standard 180 nm digital n-well CMOS process. The design consists of very less number of transistors, hence the design is area optimized. Achieved open loop gain of the amplifier is 74.89 dB. The unity gain bandwidth (UGB) is 7.3 MHz and the phase margin is 48 degree with a 10 pF capacitive and 1 M ohm resistive load. The average power consumption of the amplifier is 0.402 mWand slew rate is 10 V/us. Keywords-CMOS Op Amp, Low Power, Moderate Speed II. DESIGN OF TWO-STAGE OPERATIONAL AMPLIFIERCurrently, the most widely used circuit topology for the implementation of CMOS operational amplifier is the twostage topology. This topology provides good output voltage swing, common mode range, open l...

No abstract

No abstract

No abstract

Since CMOS technology consumes less power it is a key technology for VLSI circuit design. With technologies reaching the scale of 10 nm, static and dynamic power dissipation in CMOS VLSI circuits are major issues. Dynamic power dissipation is increased due to requirement of high speed and static power dissipation is at much higher side now a days even compared to dynamic power dissipation due to very high gate leakage current and subthreshold leakage. Low power consumption is equally important as speed in many applications since it leads to a reduction in the package cost and extended battery life. This paper surveys contemporary optimization techniques that aims low power dissipation in VLSI circuits.