A 180 nm low power CMOS operational amplifier

Abstract

The desired specifications of the design are given in the Table I below.Generic block diagram of simple two-stage op amp is shown in figure 1 below. First stage consists of high-gain differential amplifier. Mostly cascading is used to enhance the gain in this stage. This stage has the most dominant pole of the system. A common source single stage amplifier is usually used as a second stage, which gives high output voltage swing. Third stage is most commonly implemented as the unity-gain source follower circuit [51. A. Topology SelectionFor high speed and high accuracy circuits, op amps with high open-loop DC gain, large output voltage swing, and high unity-gain bandwidth are required. Our target is to design an amplifier with 5 MHz unity-gain bandwidth, and a DC gain higher than 73 dB, with a 10 pF load. Topology that will surely satisfy this magnitude of DC gain is two-stage topology. Hence two-stage topology is chosen. Fig. 1. Block diagram of basic op amp [51 V out Output Buffer Single Stage Amplifier DESIRED SPECIFICATIONS OF THE DESIGNTABLE I. Differential -Amplifier I. INTRODUCTIONOperational amplifier is most versatile and fundamental building block in analog signal processing applications. The operational amplifier (Op Amp) is a high gain, DC coupled voltage amplifier with a differential input and, single or differential output to be used with negative feedback to precisely define a closed loop transfer function. The basic requirements for an op amp are sufficiently large open loop gain, large unity gain bandwidth, high input impedance, low output impedance, and high speed. These amplifiers are key elements of most of the analog subsystems, particularly in switched capacitor filters. For last few decades a CMOS implementation of analog circuits proved better than its counterparts as the same technology can be used to implement analog as well as digital building blocks on the same chip. This paper is focused on the design of two-stage unbuffered operational amplifier for use within single chip mixedsignal system. In section II, the design methodology for twostage CMOS op amp is addressed. In section III, achieved simulation results are presented. Finally, the outcomes of the design are concluded in section IV.Abstract-This paper presents the design of two-stage operational amplifier (Op Amp). The circuit was designed in standard 180 nm digital n-well CMOS process. The design consists of very less number of transistors, hence the design is area optimized. Achieved open loop gain of the amplifier is 74.89 dB. The unity gain bandwidth (UGB) is 7.3 MHz and the phase margin is 48 degree with a 10 pF capacitive and 1 M ohm resistive load. The average power consumption of the amplifier is 0.402 mWand slew rate is 10 V/us. Keywords-CMOS Op Amp, Low Power, Moderate Speed II. DESIGN OF TWO-STAGE OPERATIONAL AMPLIFIERCurrently, the most widely used circuit topology for the implementation of CMOS operational amplifier is the twostage topology. This topology provides good output voltage swing, common mode range, open l...

Design and Analysis of High Gain Low Power CMOS Comparator

“…Finally, a comparison work is tabulated among various techniques for designing the comparator, which is shown in Table 1. 475 From Figure 6 it is shown that this comparator circuit achieved lower power dissipation, which is only 2.84 µW under supply voltage 1.2 V. In this research works, the lower power dissipation is obtained by maintaing the proper transistor sizing and small capacitnace values, which helps to dissipates lower power than [12]. From Table 1, it is shown that the output gain and gain bandwidth of this research is found lower compared to [15].…”

“…4, December 2018: 471 -476 472 stage amplifier is often implemented to achieve higher gain as it provides higher output swing in the second stage [9]. It also provides better CMRR, lower power consumption and slew rate [8], [12]. However, it requires frequency compensation for stability in closed loop application where this amplifier has multiple zeros and poles [8], [11], [12].…”

“…It also provides better CMRR, lower power consumption and slew rate [8], [12]. However, it requires frequency compensation for stability in closed loop application where this amplifier has multiple zeros and poles [8], [11], [12]. Folded cascade amplifier has an advantage in providing a better power supply rejection ratio (PSRR), high speed and extensive frequency response.…”

A Versatile Design of Low Power and High-Speed Operational Amplifier using Nano Scale Transistors

“…In paper [4] Ketan. J. Raut represented the design of two-stage op-amp using standard 180nm technology and achieved the parameter.…”

Two‐stage op‐amp and integrator realisation through GaAsP/AlGaSb nanowire CP‐TFET

“…It can be considered as a power efficient and moderate speed op-amp as it achieves a power dissipation of 6.79 μW and a slew rate of 40.56 V/μs. If we compare these results with MOSFET op-amp shown in [41], our TFET-based simulation provides better result in almost every aspect, making it desirable to replace MOSFET in analogue applications in the near future. However, it is also necessary to first build a compact model for TFET to make it more realistic in terms of analogue and digital applications.…”