International audienceLifetime estimation in Wireless Sensor Networks (WSN) is crucial to ensure that the network will last long enough (low maintenance cost) while not being over-dimensioned (low initial cost). Existing solutions have at least one of the two following limitations: (1) they are based on theoretical models or high-level protocol implementations, overlooking low-level (e.g., hardware, driver, etc.) constraints which we find have a significant impact on lifetime, and (2) they use an ideal battery model which over-estimates lifetime due to its constant voltage and its inability to model the non-linear properties of real batteries. We introduce a method for WSN lifetime estimation that operates on compiled firmware images and models the complex behavior of batteries. We use the MSPSim/Cooja node emulator and network simulator to run the application in a cycle-accurate manner and log all component states. We then feed the log into our lifetime estimation framework, which models the nodes and their batteries based on both technical and experimental specifications. In a case study of a Contiki RPL/6LoWPAN application, we identify and resolve several low-level implementation issues, thereby increasing the predicted network lifetime from 134 to 484 days. We compare our battery model to the ideal battery model and to the lifetime estimation based on the radio duty cycle, and find that there is an average over-estimation of 36% and 76% respectively

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International audienceUsing the multiple reference frames compensation in the H264 coder improves the coding efficiency for sequences which contain uncovered backgrounds, repetitive motions and highly textured areas. Unfortunately this technique requires excessive memory and computation resources. In this article, we proposed and implemented a technique based on Markov Random Fields Algorithm relying on robust moving pixel segmentation. By the introduction of this technique, we were able to decrease the number of reference frames from five to three while keeping similar video coding performances. The coding time decreased by 35% and the sequence quality was preserved. After the validation of our idea, we evaluated the processing time of the Markov algorithm on architectures intended for embedded multimedia applications. Both DSP and FPGA implementations were explored. We were able to process 50 frames(128 × 128)/s on the EP1S10 FPGA paltform and 35 frames(128 × 128)/s on the ADSP BF533

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