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Today low power implementation in the modern system on chips requires a holistic and concurrent approach which includes collaboration between power modeling and soft ware hardware co-design. Power gating is one of the emerging low power design techniques used in all the portable devices.The main goal of power gating is to eliminate the leakage current in standby mode. When the functional unit is powered on, a large and sudden inrush current is prompted through a low resistance path to ground. If' this current is excessive, then the produced surge may cause IR voltage drops and electromigration. This has a negative impact on circuit reliability and performance. Therefore an estimation of this maximum current during power up is essential for designing reliable and high performance CMOS combinational circuits. This paper describes important considerations of the high-level synthesis technique on the maximum power on inrush current. Based on this perception, a satisfiability (SAT) based approach is proposed in this paper. The problem of scheduling and functional unit binding is formulated as a satisfiability problem (SAT) and a PB SAT solver is utilized for discovering the optimal binding solution that minimizes the inrush current at the high level synthesis stage itself in the circuit design process.

A possible solution to handle the rising complexity of modern Systems-on-Chip (SoCs) is to raise the level of abstraction for the design and optimization. A better optimization of performance and power can be achieved at higher abstraction levels by applying suitable optimization techniques. Insertion of clock gating logic into the generated Register-Transfer Level (RTL) would facilitate lowering dynamic power consumption by switching off the clock signal to portions of the circuit not currently in use and thereby reducing unnecessary toggling. In this work, we have tried to minimize the power consumption of synchronous circuits by reducing the number of activity string patterns. Activity-driven clock trees have been used wherein sections of the clock tree are turned off by gating the clock signals. Since gating the clock signal implies additional control signals and gates, there is always a trade-off existing between the logic circuit area overhead and the total power consumption of the clock tree. A pseudo-Boolean satisfiability (PB-SAT)-based approach is proposed in this work which focuses on the reduction of power consumption by reducing the activity pattern of the clock tree which will reduce the power consumption with appropriate module-binding solutions.

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