Design of Network on chip architectures for multimedia applications is being widely studied. This involves design decisions at various levels of hierarchy. Topology design is one of the significant factors that affect the net delay and the energy consumption of the system. Most of the applications are characterized by bandwidth requirements and latency constraints. The topology must be built satisfying these constraints. The paper aims in generating low energy tree based topologies using homogeneous routers for bandwidth and latency constrained applications.

This study applied the finite element method (FEM) to pricing options. The FEM estimates the function that satisfies a governing differential equation through the assembly of piecewise continuous functions over the domain of the problem. Two common representations, a variational functional representation, and a weighted residual representation are used in the application of the method. The FEM is a versatile alternative to other popular lattice methods used in option pricing. Advantages include the abilities to directly estimate the Greeks of the option and allow nonuniform mesh construction. As an illustration of the advantages that the FEM offers, the method was used to price European put options and discrete barrier knock‐out put options. © 2001 John Wiley & Sons, Inc. Jrl Fut Mark 21:19–42, 2001

Reconfigurable computing (RC) systems based on FPGAs are becoming an increasingly attractive solution to building parallel systems of the future. Applications targeting such systems have demonstrated superior performance and reduced energy consumption versus their traditional counterparts based on microprocessors. However, most of such work has been limited to small system sizes. Unlike traditional HPC systems, lack of integrated, system-wide, parallel-programming models and languages presents a significant design challenge for creating applications targeting scalable, reconfigurable HPC systems. In this paper, we introduce and investigate a novel programming model based on Partitioned Global Address Space (PGAS), which simplifies development of parallel applications for such systems. The new multilevel PGAS programming model captures the unique characteristics of these systems, such as the existence of multiple levels of memory hierarchy and heterogeneous computation resources. To evaluate this multilevel PGAS model, we extend and adapt the SHMEM programming language to become what we call SHMEM+, the first known SHMEM library enabling coordination between FPGAs and CPUs in a reconfigurable, heterogeneous HPC system. Our design of SHMEM+ is highly portable and provides peak communication bandwidth comparable to vendor-proprietary versions of SHMEM. In addition, applications designed with SHMEM+ yield improved developer productivity compared to current methods of multi-device RC design and achieve a high degree of portability.

No abstract

No abstract