Low Energy Tree Based Network on Chip Architectures Using Homogeneous Routers for Bandwidth and Latency Constrained Multimedia Applications

Majeti, Deepak; Pasalapudi, Aditya; Yalamanchili, Kishore K.

doi:10.1109/icetet.2009.139

Cited by 8 publications

(5 citation statements)

References 8 publications

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“…In this technique, first an energy-aware mapping is formulated, and then a recursive bipartitioning algorithm is used to solve it. An application mapping heuristic was proposed by Majeti et al (2009) for generating an optimal tree-based topology for multimedia applications to minimize energy consumption while meeting the design constraints. Application mapping techniques were proposed by Sahu et al (2011aSahu et al ( , 2011b to map applications onto butterfly fat tree-and mesh-of-tree-based NoCs, respectively.…”

Section: Other Constructive Strategiesmentioning

confidence: 99%

Network-on-Chip

Kundu¹,

Chattopadhyay²

2018

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This book contains information obtained from authentic and highly regarded sources. Reasonable efforts have been made to publish reliable data and information, but the author and publisher cannot assume responsibility for the validity of all materials or the consequences of their use. The authors and publishers have attempted to trace the copyright holders of all material reproduced in this publication and apologize to copyright holders if permission to publish in this form has not been obtained. If any copyright material has not been acknowledged please write and let us know so we may rectify in any future reprint.The Open Access version of this book, available at www.taylorfrancis.com, has been made available under a Creative Commons Attribution-Non Commercial-No Derivatives 4.0 license.

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Section: Other Constructive Strategiesmentioning

confidence: 99%

Network-on-Chip

Kundu¹,

Chattopadhyay²

2018

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“…The author evaluated the proposed method by testing a few benchmark applications. Four various heuristic based algorithms were proposed [15] for generating the low energy tree based topology for multimedia applications. Four phase custom topology generation algorithm [16] was proposed for ASNoC.…”

Section: Related Work For Custom Topology Generationmentioning

confidence: 99%

Design of Reliable Custom Topology for Application Specific Network-On-Chip

Maheswari¹

2015

IJAREEIE

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ABSTRACT:In this paper, Reliable custom topology for Application Specific Network-on-Chip (ASNoC) which consumes less area and power consumption with high data protection (error free) is proposed. The proposed design is achieved in two steps. First a custom topology is designed for ASNoC. Second, to improve the reliability of the custom topology, three novel error correction mechanisms have been designed and incorporated in the custom topology. The proposed three error correction codes consume less are and power consumption with high error correction capability compared to the existing error correction codes. Finally the proposed error correction codes are embedded in the custom topology to generate reliable custom topology. Cadence RTL encounter tool has been used for the analysis. The generated custom topology achieves 90% & 40% reliability improvement on data through on chip inter connects in low noise and in high noise environment respectively.

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“…Different partitioning schemes, which were presented for 3D NoC architecture generation, were surveyed and evaluated in [36]. Fourth, for multimedia and other bandwidth constrained applications, network partitioning techniques were used in [37] to build a low energy treebased architecture that is suitable for these applications. A similar study was presented in [38] that combines network partitioning with a Rectilinear Steiner Tree (RST) algorithm to reduce the power consumption of NoC-based systems.…”

Section: Related Workmentioning

confidence: 99%

Networks-on-Chip Architecture Customization using Network Partitioning: A System-Level Performance Evaluation

Morgan¹

2015

IJCDS

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Networks-on-Chip (NoC) design is a trade-off between cost and performance. To realize the best trade-off between these factors, researchers have recently proposed using network partitioning techniques to customize the NoC architecture according to the application requirements. In this paper, the impact of using partitioning on different NoC metrics; namely, power, area, and delay, is analyzed. We present a system-level methodology to evaluate the performance of using partitioning-based architecture customization techniques with NoC. Our methodology is applied onto synthetic traffic as well as a number of real NoC benchmarks with different number of cores. Finally, we mathematically formulate evaluation factors that could be used as measures of the enhancements achieved by using partitioning.

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Low Energy Tree Based Network on Chip Architectures Using Homogeneous Routers for Bandwidth and Latency Constrained Multimedia Applications

Cited by 8 publications

References 8 publications

Network-on-Chip

Network-on-Chip

Design of Reliable Custom Topology for Application Specific Network-On-Chip

Networks-on-Chip Architecture Customization using Network Partitioning: A System-Level Performance Evaluation

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