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Using a trench isolated 650 V quasi-vertical n-channel DMOS as a starting point several new 650 V transistor types have been evaluated. Mainly by design measures a 650 V depletion DMOS, a 650 V PMOS and a 650 V IGBT were created for a modular integration into the process flow. Design modifications like increased channel length, well constructions and drain modifications were used to create the new devices.Original n-channel DMOS design features like curvatures or field plate constructions have been re-used. Necessary new process steps for the depletion transistor and for the IGBT were kept to minimum additional process effort and use a flexible process approach with independent addable modules. Keywords-High voltage transistor, Trench, SOI I. MOTIVATIONThe trench isolated SOI technology [1] allows not only the easy high side and/or below ground operation of logic blocks and high voltage transistors, it also allows the use of minority carrier injecting devices [2], [3]. With these preconditions numerous different 650 V transistors are desirable to address different applications. Starting point of the development was a 650 V n-channel DMOS transistors. With several design modifications in the channel and the drain region, adaptations of the field plate concepts and by using new implant steps only if necessary a series of new high voltage devices have been developed. For cost reasons the main effort was put on design modifications. Necessary new process steps should be added in a modular, cost effective and flexible way. II. STARTING POINTThe enhancement mode n-channel DMOS transistor in Fig. 1 was the starting point for the development of further high voltage devices. This nDMOS is similar to a planar vertical DMOS structure with regards to the source and channel structure but the whole device is isolated by the BOX (Buried OXide) of the SOI wafer and the isolation trench. The current flows from the channel regions vertically towards a highly n doped buried layer and is re-routed to a front side contact by a sinker doping in the trench sidewall. With this DMOS transistor typical breakdown voltages of 750 V are achieved. III. RESULTS A. HIGH VOLTAGE DEPLETION DMOSMost design elements of the n-channel HV DMOS structure are re-used to create the depletion DMOS device (e.g. edge termination field plates, dopings etc.). Only change is an additional channel implant to shift the threshold voltage and to create the normally-on behavior. With such an additional channel implant the threshold voltages can be shifted as it is shown in Fig. 2 for different layout variants.Main challenge of such a depletion DMOS is to maintain a breakdown voltage above 700 V. Inserting only the additional channel implant leads to a reach-through of the blocking potential to the source region and thus to a reduced blocking behavior, Fig. 3. This must be compensated by a design change Figure 1: quasi vertical n-channel enhancement DMOS isolated with trench and buried oxide

The successful optimization and characterization of a deep trench isolation in a thick SOI process for operating voltages up to 650 V is reported. Different technologies were investigated to optimize the mechanical stress during wafer processing and to increase the breakdown voltage of a single trench configuration. Comprehensive electrical characterization was done to investigate achievable operating conditions and related reliability issues for thick oxide trench isolation layers. The most promising trench technology was choosen as a modular extension to an existing 650 V SOI BCD process.