Blade sawing has been widely used in semiconductor industry and it is the most conventional process in semiconductor manufacturing to produce singulated ICs. This well established dicing technique poses challenges to process next generation of wafer when the wafer fabrication technology is fast scaling down in node size to 90-, 45-, 32and 22-nm where low-k dielectric is used. ILD (Inter-Layer Dielectric) and metal layers peelings, cracks, chipping, and delamination are the most common dicing defects observed on low-k wafer processed by the traditional blade sawing techniques. This paper presents an experimental study to improve the dicing performance and quality on processing low-k wafer by using a combination of laser grooving process and traditional blade sawing technique. Some low-k wafers were used as test vehicles. The laser process outcomes and responses are governed by the changes of process input parameters such as laser power, repetition rate, grooving feed speed, defocus amount and street index. The effects of the process parameters on the laser kerf geometry, grooving edge quality and defects are evaluated by using optical microscopy and scanning electron microscopy (SEM). Experimental results have shown that the dicing quality produced by using a combination of laser grooving and blade sawing technique can significantly minimize the dicing defects. It is one of the potential solutions to address the quality and yield issues in low-k wafer dicing. The key challenges of laser grooving and recommended future development works are discussed.

This paper presents an investigation on the effect and optimization of machining parameters for 90nm low-k wafer topside peeling improvement in mechanical dicing operation. It is part of the continuous improvement that performed based on current established dicing recipe. The resulted outcomes to achieve are cut quality improvement, dicing yield loss reduction and device reliability enhancement for low-k wafer dicing. The experimental studies were conducted under varying table speed, Z1 spindle rotation as well as the Z1 cut depth was examined. The settings of machining parameters were determined by using design of experiment (DOE) techniques and the critical process parameters were determined and analyzed statistically by using analysis of variance (ANOVA). Optical visual inspection was conducted on post-processed low-k test wafers and several of scribe structures which comprised of different level of metal density, for a through quantification and categorization on the peeling mode. Worst case peeling measurements and characterizations were conducted by using optical microscope, scanning electron microscopy (SEM) and focused ion beam (FIB). Electrical test and device reliability assessments were conducted to reflect and confirm the improvement of the samples diced with optimized mechanical dicing process. As a result, the optimum dicing parameters to apply in production environment was realized and established in order to overcome the quality obstacles and yield loss issue in low-k wafer dicing.

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