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Undocumented and faulty CPU instructions can cause undefined behavior and system instability, impairing software efforts such as OS crash recovery and resilience, and system security. Although often not considered, the identification of such undocumented instructions is critical. We present a portable RISC instruction scanner that is able to search for undocumented instructions on a wide range of RISC architectures, empowering users to verify the reliable and secure operation of their systems. We propose two methods to look for undocumented instructions. Both attempt to execute a single instruction word in a controlled manner, regaining control afterwards. Subsequently, we determine if the instruction word is considered valid by the processor, comparing this result to the processor's ISA specification. Our prototype scanner can scan multiple ARMv8 and RISC-V systems. Various inconsistencies were discovered in the QEMU emulator and disassemblers used as ground truth. Furthermore, we found an undocumented instruction on a RISC-V chip.

In the last decade, improvements on single-core performance of CPUs has stagnated. Consequently, methods for the development and optimization of software for these platforms have to be reconsidered. Software must be optimized such that the available single-core performance is exploited more effectively. This can be achieved by reducing the number of instructions that need to be executed. In this article, we show that layered database applications execute many redundant, nonessential, instructions that can be eliminated without affecting the course of execution and the output of the application. This elimination is performed using a vertical integration process which breaks down the different layers of layered database applications. By doing so, applications are being reduced to their essence, and as a consequence, transformations can be carried out that affect both the application code and the data access code which were not possible before. We show that this vertical integration process can be fully automated and, as such, be integrated in an operational workflow. Experimental evaluation of this approach shows that up to 95% of the instructions can be eliminated. The reduction of instructions leads to a more efficient use of the available hardware resources. This results in greatly improved performance of the application and a significant reduction in energy consumption.

To improve the effectiveness and efficiency of optical projection tomography (OPT) 3-D reconstruction, we present a fast post-processing pipeline, including cropping, background subtraction, center of rotation (COR) correction, and 3-D reconstruction. Regarding to the COR correction, a novel algorithm based on interest point detection of sinogram is proposed by considering the principle of OPT imaging. Instead of locating the COR on single sinogram, we select equally spaced sinograms in the detected full range of specimen to make the located COR more convincing. The presented post-processing pipeline is implemented in a parallel manner and the experiments show that the average runtime for each image of size 1036 ×1360 ×400 pixels is less than 1 min. To quantify and compare the reconstructed results of different COR correction approaches, the coefficient of variation instead of variance is employed. The results indicate that the proposed COR correction outperforms the three traditional COR alignment approaches in terms of effectiveness and computational complexity.

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