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An all-digital delay-locked loop (ADDLL) is proposed for wide range, fast lock, low jitter and high process-voltage-temperature (PVT) tolerance. The proposed phase tracking generator (PTG) produces two tracking rising and falling phases in only 2 cycles for fast lock and wide-range. The digital phase interpolator (DPI) and the control block are adopted to calibrate the phase offsets and random jitters while maintaining the closedloop property that allow for tracking of PVT variations. The wide-range ADDLL operates from 160MHz to 2GHz. The measured peak-to-peak jitters are 6.89ps and 16.67ps at 2GHz and 160MHz. This chip is fabricated in TSMC 90nm CMOS technology with an active area of 0.205mm 2 .

In this paper, a wide range and low power multi -rate receiver for DisplayPort Version 1.3 is proposed. In order to extend the bandwidth, a high speed AC coupled interconnect receiver comprising output compensated negative impedance and positive feedback techniques is introduced. Furthermore, the automatic bit-rate tracking scheme is used for clock and data recovery (CDR) to achieve wide data rate range. Besides, this wide range CDR is realized by omitting the power-hungry divider. Thus, the required area and the corresponding power consumption can be substantially reduced. Designed and fabricated in 90nm CMOS technology, this test chip occupies 0.23 mm 2 and consumes 90 mW. The measured root-mean-square jitter is 5.52/3.15/2.96/3.6 ps rms with the data rates of 8.1/5.4/2.7/1.62 Gb/s, respectively. The bit error rate (BER) for all data rate is less than 10 -12 for 2 7 -1 pseudo random binary sequences (PRBS).