DFM considerations have become an indispensable and integral part of advanced nanometer semiconductor product designs. Traditional first-generation DFM tools have focused on functional lithography hotspot detections. While useful, these tools offer designers few hints on the complex layout fixings and the intricate trade-off decisions required. With these limitations, DFM layout optimization has become a tedious and inconsistent design endeavor. In addition, the long and intense calibration cycle required for the traditional DFM models have hindered their effectiveness and timeliness. An automatic DFM layout optimization system that performs systematic multi-objective functional and parametric DFM optimizations at early design phase will be introduced. A calibration-lite methodology that has expedited the DFM model set-ups will be discussed along with the silicon validation test pattern designs. Finally, both simulation and silicon experiment results will be presented. MOTIVATIONThere are several challenges in optimizing a layout to improve its design for manufacturability (DFM). First, traditional lithography hotspot information, which can be acquired by many simulation-based tools operating on a single layer of layout 1,2 , offer designers few hints on how to actually improve the layout. Usually such hotspots appear in the layout at positions where the optical proximity correction (OPC) engine or recipe has reached its limits and can no longer correct the layout throughout its full required process window. An attempt to remove a hotspot by movement of e.g. the closest polygon-edges can very likely introduce new hotspots as a consequence of the strongly non-linear and non-intuitive effects that deep sub-wavelength lithography conditions induce. Such new hotspots could appear either within the layer of consideration but also in one of the other layers because of the interrelation enforced by design rules. For instance, solving a hotspot in the poly layer could lead to a hotspot in the metal1 layer. Second, hotspots often occur in dense, non-regular layout and a fix will have a large range of influence rippling through the layout in multiple directions and affecting a large amount of polygon edges. It is virtually impossible to do this by manual layout editing. Third, lithography hotspots are not the only mechanism that can limit device performance, yield and wafer manufacturability. There are many other systematic and random loss mechanisms that will be mutually competing such as overlay-margin, vulnerability of the device to opens and shorts caused by random defects ("CAA"), transistor variability properties affecting speed, leakage, and parasitic capacitances, etc.Takumi Technology Corporation's Takumi Enhance ("TKE") is the first commercially available software tool that addresses all the issues above. The tool can automatically optimize physical layout for multiple systematic and random loss-mechanisms that are competing with each other with control by a user-specified trade-off balance.In this paper we prese...

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The sections in this article are General Methods For Yield Improvement in Semiconductor Manufacturing Monitoring and Diagnosis at The Unit Process and Equipment Level Monitoring/DIagnosis at the Process Flow Level