A low‐chip area and low‐phase noise phase‐locked loop (PLL) combining fractional‐N and integer‐N modes operating at 2.4 GHz band is proposed and fabricated in TSMC 0.18‐μm CMOS process.The proposed PLL with a Gm‐boosted Colpitts voltage‐controlled oscillator improves phase noise and a hybrid design of different divider loops achieves fast lock. At 1.8 V supply voltage, the proposed PLL shows a wide tuning range from 2.14 to 2.36 GHz, corresponding to 9.7%, a phase noise of −119.3 dBc/Hz at an offset frequency of 1 MHz from the carrier frequency of 2.14 GHz, a power consumption of 17.3 mW, and an output power of −15.37 dBm. Including pads, the chip area only occupies 0.588 (0.87 × 0.67) mm2. © 2012 Wiley Periodicals, Inc. Microwave Opt Technol Lett 54:2295–2300, 2012; View this article online at wileyonlinelibrary.com. DOI 10.1002/mop.27082

A fully integrated CMOS Hartley voltage controlled oscillator (VCO) applying in 5.6 GHz wireless receiver communication is successfully implemented by TSMC 0.18‐μm CMOS process.To reduce the phase noise, the proposed VCO adopts the tapped‐inductor technique, differential architecture, and symmetrical layout. No more integrated inductors are used for the buffer design to avoid magnetic coupling into the VCO core. At the supply voltage of 1.3 V, measured results achieve a tuning range of 5.38 to 5.55 GHz with a tuned voltage of 0 to 1.3 V, a phase noise of −115.4 dBc/Hz at 1 MHz frequency offset from the carrier frequency of 5.55 GHz and an output power of −6.3 dBm at 5.55 GHz. The power dissipation of the VCO is 3.77 mW and the chip area, including pads, is 0.51 (0.55 × 0.93) mm2. © 2013 Wiley Periodicals, Inc. Microwave Opt Technol Lett 55:978–981, 2013; Microwave Opt Technol Lett 55:978–981, 2013; View this article online at wileyonlinelibrary.com. DOI 10.1002/mop.27506

A new fully integrated, low power complementary cross-coupled quadrature voltage-controlled oscillator (QVCO), divide-by-two frequency divider and double-balance mixer for biomedical applications are presented. The features of our proposed circuit are using charge recycling technique to reduce current from the divider, employing adaptive body-biasing technique (ABB) to drop the minimum voltage clearance of the VCO and achieving two quadrature frequencies which are 2.0 GHz and 4.0 GHz bands. The VCO use differentially tuned MOS varactors can diminish the bad effect of high varactor sensitivity by excluding the common-mode noise. The proposed QVCO and double-balance mixer were implemented in 0.18 um CMOS process with 1. V supply voltage, is employed to modulate a wireless communication signal for proposed interactive intelligent healthcare monitoring system (IIHMS). Measured results indicate the divider output frequency is tunable from 1.91GHz to 2.07 GHz and the QVCO output is from 3.82 GHz to 4.14 GHz, corresponding to 8.05 %. The phase noise of the QVCO operating at 2.02 GHz is -121.8 dBc/Hz at 1 MHz offset. This QVCO draws 2.61 mA and 4.7 mW power consumption. The output power is -17.15 dBm with a 50-Ω load at the frequency of 2.02 GHz. The broadband CMOS double-balance mixer input return loss is higher than 8.5 dB.

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