Porous Si is the semi-insulating state of Si, with low thermal expansion mismatch with bulk Si. As a result, it is an excellent material for crosstalk isolation in mixed-signal integrated circuits. We study the formation of isolated porous Si regions in p−-type and p+-type Si substrates with emphasis on the cross-sectional profile of the porous regions. Our study reveals that in addition to the primary undercut due to the isotropic nature of the anodization process, there exists a secondary undercut that is similar in shape to the bird’s beak commonly observed at the edge of field oxides in conventional Si complementary-metal-oxide-semiconductor process. The shape and the extent of the secondary undercut are dependent on the type of mask materials used during selective formation of porous Si as well as the substrate resistivity. The combined experimental and simulation studies pointed to two likely origins of secondary undercuts: the weak adhesion of some of the mask materials and current crowding in bulk Si substrates near the edge of the mask openings. Secondary undercuts result in the erosion of the precious Si chip surface area when a porous Si trench is used for rf crosstalk isolation, and should be minimized.

A novel approach using unoxidized porous Si (UPS) as an isolation material for mixed-signal integrated circuit applications is presented. Very thick PS can be locally fabricated without severe stress problems. Relative dielectric constants of PS are adjustable from 3 to 9 by changing porosity from 78% to 24%. PS with more than 51% porosity has low loss tangent (<0.001) at 20 GHz demonstrating the superior dielectric material for RF ranges. PS trench inserted between two signal pads is shown to provide effective suppression of crosstalk through substrates. On-chip inductors built on porous Si regions have a Q max of 29 at 7 GHz and a resonant frequency that is higher than 20 GHz. Superb and controllable dielectric properties as well as mechanical integrity of porous Si have clearly demonstrated its promising role among various RF isolation materials for mixed-signal integrated circuits and system-on-chip.

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To study the substrate effect on inductor performance, several types of spiral inductors were fabricated on porous silicon (PS), p and p + silicon substrate. -network analysis results show that the use of PS effectively reduces the shunt conductance and capacitance. The analysis further shows that the use of PS significantly reduces the eddy current portion of series resistance of inductor, leading to slower increase of the apparent series resistance with increasing frequency. Higher -factor and resonant frequency ( ) result from the reduced shunt conductance, shunt capacitance, and frequency dependence of series resistance. Inductors fabricated on PS regions are subjected to a much less stringent set of constraints than those on bulk Si substrate, allowing for much higher inductance to be achieved without severe sacrifice in -factor and . Similarly, much higher -factor can be obtained for reasonable inductance and .Index Terms-Eddy current, on-chip inductor, porous Si, quality factor, substrate effect.