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A fully integrated digital LC I'LL for low jitter frequency synthesis in a standard digital 130nm CMOS technology is presented, The PLL features aQIly digital core and a digitally controlled LC oscillator. It supports triple-band operation in multi-GHz range (2. lGHz, 3.3GHz and 4.4GHz) with a single programmable coil, resulting in a die area as small as 0.24mm2. While consuming 16mA of current, the PLL achieves an outstanding long-term jitter of 640f, which compares with the most advanced analog PLLs. Its digital nature makes it easily implementable in the main stream digital CMOS technologies, robust against noise and thus ideul for application as low jitter clock multiplying unit in digital intensive systems on chip (SoCs).

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