Extending the applicability of Teachability analysis t o large and real circuits is a k e y issue. In f a c t they are still limited for the following reasons: peak B D D size during image computation, B D D explosion for representing state sets a n d very high sequential depth. Following the promising trend o f partitioning and problem d ecomposition, we present a new approach based on a disjunctive partitioned transition relation and on a n improved iterative squaring. In this approach a Finite State Machine is decomposed and traversed one 'ifunctioning-mode" at a tame b y means of the "disjunc-live" partitioned approach. The overall algorithm aims at lowering the intermediate peak BDD size pushing further Teachability analysis. Experiments on a few industrial circuits containing counters and on s o m e large benchmarks show the feasibility of the approach.

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