Shrinking geometries and greater use of automatic board assembly equipment put greater demands on the ESD input protection structures. To achieve high levels of protection requires an understanding of structures work, and how transient which part of the circuit is damaged. structure for CMOS is presented.

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Electrostatic discharge (ESD) was once considered a problem only for unprotected, insulated-gate field-effect transistors, but the ever shrinking geometries of all semiconductor devices have made them vulnerable to this phenomenon. ESD models and on-chip device protection techniques are reviewed, together with current evidence concerning latent defects and their effect on device reliability. A brief discussion on the importance of ESD controls in the assembly environment is also included, with an emphasis on realistic cost-effective measures. Finally, the impact of continued scaling on ESD vulnerability and protection structure limitations, are examined.

St . Boulder City. NV 89005, USA Abstrirct -The ESD Association standards workinig group 5.3.2 is analvzing the procedure and stress that is applied to a device under test (DUT) using a socketed discharge model (SDM) test system, formerly referred to as socketed CDM. Our tinal goal is to define an SDM tester specification that ill guarantee test result reproducibility across different test equipment. This paper investigates the effect of tester background parasitics on the discharge current waveforms of an SDM tester. Characteristic waveforms were studied and SDM testing was performed on actual devices. It is shown that SDM tester parasitics determine the stress applied to the DUT. This directly impacts the SDM failure threshold voltage levels and may llead to miscorrelation and non-reproducibility of test results across different SDM test systems. This paper empirically determines the relative contributions of the various tester parasitics to the total stress applied to the DUT. Our investigations indicate that the tester provides a lOpF to 20pF parasitic capacitance discharge into each pin of the device. Tester background parasitic elements play such an important role in the SDM discharge event that correlation between test systems built by different manufacturers is unlikcl\. without completely duplicating a particular tester

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