A critical component of ultrahigh-speed Josephson logic systems is compatible memory. We are developing a fast Josephson memory that could be used as a small memory or first-level cache. Performance goals include sub-ns access and cycle time, 16 kbit cm-2 integration scale, low power consumption and appreciable yield. Initial test results on circuits fabricated in TRW's standard Nb integrated circuit process indicate that all these goals may be achieved. A 5 bit parallel decoder and 1 kbit memory array have been tested at 0.5 GHz. The maximum operating frequency of the memory array was limited by the test equipment. Circuit density is consistent with 16 kbit cm-2. The top-level architecture has been chosen to achieve high throughput and low skew. The architecture is word organized, multiported and interleaved.

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