GHz. Figure 6(b) shows the measured phase noise of the injection signal and locked output signal for the divide-by-2 ILFD. At 100 KHz offset frequency, the phase noise of the injection signal is Ϫ100.6 dBc/Hz, and the phase noise of the locked signal is Ϫ106.8 dBc/Hz. At low offset frequency, the phase noise of the locked output spectrum is lower than that of injection reference by 6.2 dBc/Hz. Figure 7 shows the measured time-domain output waveforms from two QILFD output buffers by using the Agilent 54855A Infiniium oscilloscope. The average output phase error is about 0.28°introduced partly by cables and connectors. Table 2 is the performance comparison of the existing QILFDs. Figure 8 shows the measured relationship between input sensitivity and operating frequency of the divide-by-2 QILFD at V dd ϭ 0.7 V. The locking range is from 9.9 to 11.1 GHz at the input power of 0 dBm and V bias ϭ 0.6 V and the power is 3.37 mW. CONCLUSIONIn this paper, a new LC-tank divide-by-2 QILFD has been proposed. The QILFD consists of a back-gate coupling quadrature VCO and a pair of injection transistors for coupling injection signal to the resonators. The new quadrature VCO uses two differential VCOs with different gate and drain dc biases and a back-coupling mechanism so that the power can be lowered, and the trade-off of power and locking range can be optimized by tuning the gate bias for RF application. The quadrature ILFD has been successfully implemented in the TSMC 0.18 m CMOS process. At the supply voltage of 0.8 V and gate bias ϭ 0.7 V of switching MOSFETs, the core power consumption of the proposed circuit is about 5.72 mW. At the input power of 0 dBm, the total operation locking range is 5.1 GHz, from 8.2 to 13.3 GHz, in the divide-by-2 mode. The phase deviation between in-phase and quadrature-phase outputs is about 1.28°. CENTER-FED CIRCULAR EPSILON-NEGATIVE ZEROTH-ORDER

This paper presents a physical derivation of phase noise in source-coupled-logic frequency dividers. This analysis takes into account both white and flicker noise sources and is verified on two 32/33 dual-modulus prescalers integrated in a 0.35-μm CMOS process. Design techniques for high-speed and low-noise operation are provided. The two integrated prescalers are identical apart from a synchronizing flip-flop at the output of one of them. The measured phase spectra are in good agreement with the estimates and demonstrate that the final synchronization allows a better trade-off between noise and power consumption. The maximum operating frequency is 3 GHz, the power consumption is 27 mW and the phase noise floor is -163 dBc/Hz referred to the 78-MHz output

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This paper proposes a complete analysis of quadrature-coupled LC oscillators. These oscillators operate off-resonance and for this reason, their phase noise worsens at increasing coupling strength. Since the coupling transistors raise the total power consumption, the noise-power product degrades further with respect to a stand-alone oscillator. On the other hand, at high coupling factors component mismatches affect less the phase accuracy of the quadrature outputs. Closed-form expressions for phase noise and phase accuracy are derived which are verified against circuit simulations.

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