Pairwise sequence alignment is ubiquitous in modern bioinformatics. It may be performed either explicitly, e.g. to find the most similar sequences in a database, or implicitly as a hidden building block of more complex methods, e.g. for reads mapping. The alignment algorithms have been widely investigated over the last few years, mainly with respect to their speed. However, no attention was given to their energy efficiency, which is becoming critical in high performance computing and cloud environment. We compare the energy efficiency of the most established software tools performing exact pairwise sequence alignment on various computational architectures: CPU, GPU and Intel Xeon Phi. The results show that the energy consumption may differ as much as nearly 5 times. Substantial differences are reported even for different implementations running on the same hardware. Moreover, we present an FPGA implementation of one of the tested tools -G-DNA, and show how it outperforms all the others on the energy efficiency front. Finally, some details regarding the special RECS R |Box servers used in our study are outlined. This hardware is designed and manufactured within the FiPS project by the Bielefeld University and Christmann Informationstechnik + Medien with a special purpose to deliver highly heterogeneous computational environment supporting energy efficiency and green ICT.

The abstraction level of designing digital circuits is rising since high-level synthesis tools are gaining acceptance and are available from different vendors. Simultaneously, the demand for accurate energy estimations on higher abstraction levels is increasing. But estimating energy on these abstraction levels is a difficult task since switching capacitances and area depend on scheduling and allocation decisions which are made during high-level synthesis.In this paper a current energy estimation methodology is extended by a power estimation approach to enable energyaware design designs on behavioural level. The energy estimation uses control-flow information to model energy and runtime of a component while the power estimation approach generates power and protocol state machines by monitoring external port behaviour and putting it in relation to power dissipation. The methodology is evaluated for a linear predictive coding algorithm receiving its input data from a memory block which is provided as a black-box IP-component. By using the presented estimation methodology, it can be decided at behavioural level whether the usage of this memory element violates a given power budget. The average estimation error for energy is 12.55% while runtime can be estimated with an error of 1.5% .

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