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Power dissipation is one of the key parameters when designing digital circuits. While an ASIC can be exactly fitted to the requirements, targeting an FPGA means to select one of many commercially available FPGAs having different power characteristics.In this work an approach for scaling existing power values from one FPGA implementation to other FPGAs is presented. This enables a fast design space exploration of many different FPGA target architectures. The methodology is based on characterising the most important properties of each relevant FPGA type using some test designs. Afterwards, a modelling process is started for each aspect of power dissipation. The model is evaluated using a secure hashing algorithm and a Viterbi codec as benchmark designs. The mean absolute relative error for the total dynamic power dissipation is 7.3% while static power can be modelled nearly perfectly with a mean error below 0.01%.The methodology can be used to choose the most powerefficient target FPGA for an existing design without executing the traditional power estimation flow for every device under consideration.

The abstraction level of designing digital circuits is rising since high-level synthesis tools are gaining acceptance and are available from different vendors. Simultaneously, the demand for accurate energy estimations on higher abstraction levels is increasing. But estimating energy on these abstraction levels is a difficult task since switching capacitances and area depend on scheduling and allocation decisions which are made during high-level synthesis.In this paper a current energy estimation methodology is extended by a power estimation approach to enable energyaware design designs on behavioural level. The energy estimation uses control-flow information to model energy and runtime of a component while the power estimation approach generates power and protocol state machines by monitoring external port behaviour and putting it in relation to power dissipation. The methodology is evaluated for a linear predictive coding algorithm receiving its input data from a memory block which is provided as a black-box IP-component. By using the presented estimation methodology, it can be decided at behavioural level whether the usage of this memory element violates a given power budget. The average estimation error for energy is 12.55% while runtime can be estimated with an error of 1.5% .

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