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This work is a contribution to high level synthesis for low power systems. While device feature size decreases, interconnect power becomes a dominating factor. Thus it is important that accurate physical information is used during high-level synthesis [1]. We propose a new power optimisation algorithm for RTlevel netlists. The optimisation performs simultaneously slicingtree structure-based floorplanning and functional unit binding and allocation. Since floorplanning, binding and allocation can use the information generated by the other step, the algorithm can greatly optimise the interconnect power. Compared to interconnect unaware power optimised circuits, it shows that interconnect power can be reduced by an average of 41.2 %, while reducing overall power by 24.1 % on an average. The functional unit power remains nearly unchanged. These optimisations are not achieved at the expense of area.

Providing health care and assistance at home becomes more and more important due to the aging society and -in general -a health system under financial pressure. It is generally accepted that these services have to be supported by an eHealth infrastructure that enables the exchange of patient related data between different health institutions and assistance systems at home (referred to by the term AAL). In this paper a service-oriented architecture for delivering eHealth / AAL services at home using a hardware platform such as a residential gateway or a set-top-box is proposed and exemplified by three different services: (1) telerehabilitation of patients after heard surgery, (2) support of hearing impaired people and (3) the monitoring of Activities of Daily Living (ADL).

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We present a software tool for power dissipation analysis and optimization on the algorithmic abstraction level from C/C++ and VHDL descriptions. An analysis is most efficient on such a high level since the influence of design decisions on the power demand increases with increasing abstraction [1]. The ORINOCO  tool enables to compare different but functionally equivalent algorithms and bindings to RT-level architectures with respect to power consumption. The results of the optimized binding can be used to guide synthesis. In the experimental evaluation we compare the predicted optimization trend with synthesized implementations and prove the accuracy of our methodology and tool.