Monolithic integration of III-V semiconductors with Silicon technology has instigated a wide range of new possibilities in the semiconductor industry, such as combination of digital circuits with optical sensing and high-frequency communication. A promising CMOS compatible integration process is rapid melt growth (RMG) that can yield high quality single crystalline material at low cost. This paper represents the study on ultra-thin InSb-on-insulator microstructures integrated on a Si platform by a RMG-like process. We utilize flash lamp annealing (FLA) to melt and recrystallize the InSb material for an ultra-short duration (milliseconds), to reduce the thermal budget necessary for integration with Si technology. We compare the result from FLA to regular rapid thermal annealing (seconds). Recrystallized InSb was characterized using electron back scatter diffraction which indicate a transition from nanocrystalline structure to a crystal structure with grain sizes exceeding 1 μm after the process. We further see a 100× improvement in electrical resistivity by FLA annealed sample when compared to the as-deposited InSb with an average Hall mobility of 3100 cm 2 V −1 s −1 making this a promising step towards realizing monolithic mid-infrared detectors and quantum devices based on InSb.

In this work, we study the electron mobility of near surface metal organic vapor phase epitaxy-grown InGaAs quantum wells. We utilize Hall mobility measurements in conjunction with simulations to quantify the surface charge defect density. Buried quantum wells are limited by polar optical phonon scattering at room temperature. In contrast, the quantum wells directly at the surface are limited by remote charge impurity scattering from defects situated at the III–V/oxide interface or inside the oxide, showing a mobility of 1500 cm2/V s. Passivating the InGaAs surface by depositing an oxide reduces the amount of defects at the interface, increasing the mobility to 2600 cm2/V s.

We present a semi self-aligned processing scheme for III–V nanowire transistors with novel semiconductor spacers in the shape of Λ-ridges, utilising the effect of slow growth rate on {111}B facets. The addition of spacers relaxes the constraint on the perfect alignment of gate to contact areas to enable low overlap capacitances. The spacers give a field-plate effect that also helps reduce off-state and output conductance while increasing breakdown voltage. Microwave compatible devices with L g = 32 nm showing f T = 75 GHz and f max = 100 GHz are realized with the process, demonstrating matched performance to spacer-less devices but with relaxed scaling requirements.