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Considering that the more information you can gather about a particular circuit, you can address problems more accurately in the Eletronic Design Automation (EDA) eld, therefore, many tools focus on obtaining the maximum amount of information about the input to which it is provided in order to determine which are the best algorithms to each instance. Some of these tools are the Boolean Satisfiability (SAT) problem solvers; which, for the most part, receive formulas described in Conjunctive Normal Form (CNF) as input. The circuits encoding process to the CNF format, unfortunately, destroy much of the information that could have been used to optimize SAT solvers, as part of this informations must be recovered to avoid applying generic algorithms in the solution of SAT problems. One of the difficult aspects of retrieving this information corresponds to the matching of clauses to its respective logic gates, as well as which sets of logic gates correlate to a functional block. The present work makes use of subgraph isomorphism algorithms to recover circuits encoded in CNF-DIMACS maximimizing the number of clauses handled, both at the level of logic gates as well as more complex structural blocks, which allow their identification at higher levels of abstraction. Our tool was able to successfully recover all circuits

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