1. Rational speed control to strike an effective balance between navigation efficiency and system safety.2. AIS data mining and innovative use for evaluating the performance of shipping traffic. 3. A new framework to explain the process of data acquisition, error elimination and combination of AIS and geocoded data. 4. Analysis of shipping traffic performance from a new perspective with respect to the characteristics of different navigational segments.5. Real case study to justify the rational ship speed limit in the Shanghai section of the Yangtze River.

No abstract

No abstract

The introduction of low-k/ultra-low-k (ULK) dielectric materials to accommodate the continuous scaling-down of the feature sizes of IC chips to improve the device density and performance of the ultra-large scale integrated (ULSI) circuits represents great silicon and packaging integration challenges due to the weak mechanical properties of interlayer dielectric material (ILD). Implementation of crackstop and improve low-k/ULK mechanical properties are very effective to protect ILD crack propagation and delamination. Finite element analysis (FEA) simulation and Shadow Moire measurements showed higher die stress with lead free bumps.Reflow simulated Shadow Moire measurements show a large warpage change from 150C to 25C, good control of the ramp rate is needed. Die warpage releases 50% after 30 days.

Power, performance, and area gains are important metrics driving the CMOS technology from older nodes to newer ones. Over past several decades, a steady downscaling of feature sizes of CMOS technology has been a leading force enabling continual improvement in circuit speeds and cost per functionality. Increase in functionality drives larger number of I/Os, and the scaling driven small IP block sizes force these larger number of I/Os to be accommodated by reduction of I/O pitches. The result is an unrelenting pressure to reduce bump pitches from one generation of CMOS to another. In contrast to 14nm/16nm nodes which used 150um bump pitch coming out of a die, for 7nm node the industry is targeting 130um bump pitch for high performance devices. With this pitch reduction, conventional SnAg solder bumps face limitations in terms of bridging. Cu pillar bumps are the best candidate for smaller bump pitches. However, for large die sizes prevalent in High Performance Computing, the Cu pillar bumps will induce higher stress on the silicon resulting in higher risks of ELK cracking. If copper pillar bumps are not properly developed, then there is a risk of marginal reliability in terms of chip package interaction. The situation becomes even more dire in large die sizes, where CTE mismatch between silicon and laminate substrate magnifies the stress. The present paper discusses successful development of Cu pillar bumps for 7nm technology. The development program included a 2-step development path. In the first step, extensive thermo-mechanical modeling was done to find optimal design of copper pillar bump for robustness of interactions with 7nm BEOL ELK layers. In the second step, a 460 mm2 7nm Silicon test Vehicle was fabricated and its assembly process was optimized to characterize the copper pillar bumps and prove their extended reliability on 7nm silicon. As a result of this development, copper pillar technology has been qualified on AMD products. Today, copper pillar is a fully integral part of AMD's ever-growing 7nm product offering in High Performance Computing.