This paper describes a 2-20 GHz 6-bit True-Time Delay. A total equivalent electrical length in air of 43.5 mm (145 ps) is achieved over a 2-20 GHz bandwidth. Digital drivers and a serial-to-parallel converter are integrated on the same MMIC. The ED02AH 0.2 µm PHEMT process from OMMIC is used. The time delay elements are real-ised using constant-R networks. The three smallest bits make use of a self-switched version of the constant -R networks while the 3 largest bits use a topol-ogy with single-pole double-throw (SPDT) switches and constant-R networks in the delay path. Measurement results for a typical chip are presented.

No abstract

A frequency doubler with pre-amplifier and driver amplifier for the LO chain of a 60 GHz communication system has been designed and tested. The circuit has been designed in conjunction with other transceiver sub-systems in the 0.15 µm GaAs pHEMT process of UMS (PH15). The measurements show good fundamental suppression of 35 dBc and an output power that can drive the co-designed mixer circuit. The doubler chain with amplifiers is approx. 3x1.3 mm, has a gain of 11 dB and a P -1dB at the output of +11 dBm.

No abstract