In this paper we present a floorplanning algorithm for 3-D ICs. The problem can be formulated as that of packing a given set of 3-D rectangular blocks while minimizing a suitable cost function. Our algorithm is based on a generalization of the classical 2-D slicing floorplans to 3-D slicing floorplans. A new encoding scheme of slicing floorplans (2-D/3-D) and its associated set of moves form the basis of the new simulated annealing based algorithm. The bestknown algorithm for packing 3-D rectangular blocks is based on simulated annealing using sequence-triple floorplan representation. Experimental results show that our algorithm produces packing results on average 3% better than the sequencetriple-based algorithm under the same annealing parameters, and our algorithm runs much faster (17 times for problems containing 100 blocks) than the sequence-triple. Moreover, our algorithm can be extended to consider various types of placement constraints and thermal distribution while the existing sequence-triple-based algorithm does not have such capabilities. Finally, when specializing to 2-D problems, our algorithm is a new 2-D slicing floorplanning algorithm. We are excited to report the surprising results that our new 2-D floorplanner has produced slicing floorplans for the two largest MCNC benchmarks ami33 and ami49 which have the smallest areas (among all slicing/nonslicing floorplanning algorithms) ever reported in the literature.

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For organic thin‐film transistors (OTFTs) made of solution processed stacks of organic semiconductor and dielectric materials, it is a grand challenge to eliminate the leakage current paths. With a top‐gate bottom‐contact structure, this work introduces a strong dipole interfacial layer made of self‐assembled monolayer (SAM) molecules at metal‐semiconductor contacts to suppress minority carrier injection for low leakage and stable operation, while not affecting majority carrier injection. Both gate insulator (GI) leakage and parasitic leakage in the device architecture are also effectively suppressed with a sputtering‐resistant polymer GI layer and photolith patterned OSC islands, respectively. The devices present a decent mobility with a typical value of 1.98 cm2 V–1 s–1, record‐low leakage current at 10–18 A µm−1 and large ON/OFF ratio (>1010) in a wide gate voltage range (100 V), reaching the theoretical limit and also the best level of inorganic counterparts despite much lower processing temperature (120 °C). Manufacturability of the material stack is verified on a 200 mm × 200 mm substrate and the fabricated 4.7 in. active‐matrix organic light‐emitting diode display, integrating more than 150 000 OTFTs, can be operated at ultra‐low frame‐rate (0.1 Hz) for power saving.

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