Floorplanning for 3-D VLSI design

Abstract

In this paper we present a floorplanning algorithm for 3-D ICs. The problem can be formulated as that of packing a given set of 3-D rectangular blocks while minimizing a suitable cost function. Our algorithm is based on a generalization of the classical 2-D slicing floorplans to 3-D slicing floorplans. A new encoding scheme of slicing floorplans (2-D/3-D) and its associated set of moves form the basis of the new simulated annealing based algorithm. The bestknown algorithm for packing 3-D rectangular blocks is based on simulated annealing using sequence-triple floorplan representation. Experimental results show that our algorithm produces packing results on average 3% better than the sequencetriple-based algorithm under the same annealing parameters, and our algorithm runs much faster (17 times for problems containing 100 blocks) than the sequence-triple. Moreover, our algorithm can be extended to consider various types of placement constraints and thermal distribution while the existing sequence-triple-based algorithm does not have such capabilities. Finally, when specializing to 2-D problems, our algorithm is a new 2-D slicing floorplanning algorithm. We are excited to report the surprising results that our new 2-D floorplanner has produced slicing floorplans for the two largest MCNC benchmarks ami33 and ami49 which have the smallest areas (among all slicing/nonslicing floorplanning algorithms) ever reported in the literature.

Low-power gated bus synthesis for 3d ic via rectilinear shortest-path steiner graph

“…Suppose there are Q pairs of masters and slaves where Q = n × m. We use (s l , t l ) to denote the l th master-slave pair. To transform the RSSG problem into an ILP, we construct a directed graph N l as in Figure 6 We use the first three constraints in (6) to guarantee the existence of a valid flow for each (s l , t l ) pair. Now let EH be the set of undirected edges in the Hanan grid and let the binary variable x uv denote whether the edge (u, v) ∈ E H is selected in the RSSG solution.…”

“…We use the fourth constraint in (6) to denote such constraints. Finally, if d uv denotes the length of edge (u, v), our objective is to minimize the total wire length which can be described by the objective function of (6). Since there are O((n + m)…”

“…Table 2 gives the total wire length improvement of our algorithms when compared with the RSSG result in [16]. The column "LP(obj)" denotes the optimal objective value of the LP relaxation in (6). The column "LP(Round)" denotes the total wire length of the LP relaxation and rounding result.…”

Placement of defect-tolerant digital microfluidic biochips using the T-tree formulation

“…To the best knowledge of the authors, our work is the first to apply a topological representation to solve the placement problem of digital microfluidic biochips. We choose the T-tree ] topological representation over other 3D representations, such as 3D-subTCG ], Sequence Triplet [Yamazaki et al 2000], and 3D slicing tree [Cheng et al 2005], because T-tree is effective and efficient on volume optimization and handling the storage units. We also explore the property of a bioassay to develop a clustering algorithm; since a generation operation and a reconfigurable operation are performed sequentially in a bioassay, we cluster the two operations a priori for better solution quality and less CPU time.…”

Physical Design Issues in 3-D Integrated Technologies

“…Most floorplanning algorithms can be classified as either slicing [25] or non-slicing [26]. Floorplanning techniques belonging to both of these categories have been proposed for 3-D circuits [27]- [29]. An efficient floorplanning technique for 3-D circuits should adequately handle two important issues; representation of the third dimension and the related increase in the solution space.…”