For the first time, this work investigated the timedependent variability (TDV) in RRAMs and its interaction with the RRAM-based analog neuromorphic circuits for pattern recognition. It is found that even the circuits are well trained, the TDV effect can introduce non-negligible recognition accuracy drop during the operating condition. The impact of TDV on the neuromorphic circuits increases when higher resistances are used for the circuit implementation, challenging for the future low power operation. In addition, the impact of TDV cannot be suppressed by either scaling up with more synapses or increasing the response time and thus threatens both real-time and general-purpose applications with high accuracy requirements. Further study on different circuit configurations, operating conditions and training algorithms, provides guidelines for the practical hardware implementation.

3D integration of vertical resistive random access memory (VRRAM) with organic materials is promising for ultra‐high density flexible data storage. However, it is extremely challenging to heterogeneously fabricate an organic 3D VRRAM due to complicated issues such as chemical/thermal robustness, compatibility of organic/inorganic materials, and processes of stacking/patterning multi‐layer organic/metal films. Herein, an organic flexible 3D VRRAM based on parylene‐C is experimentally demonstrated on a standard complementary metal oxide semiconductor platform for the first time. The proposed 3D VRRAM can be homogenously fabricated based solely on parylene‐C (except the metal electrodes), significantly facilitating the 3D integration owing to chemical stability and compatibility with standard photolithography patterning. The flexible 3D organic memory arrays demonstrate great memory characteristics including retention time >105 s, endurance cycles >300, and resistance ON/OFF ratio >10. Further, a finite element analysis is established to model and investigate the scaling potential of the organic 3D VRRAM. The simulation results indicate the elevated temperature during programming could be catastrophic for ultra‐high density 3D VRRAM if the feature size approaches ≈100 nm or below, urging the containment of programming power to avoid thermal issues as well as to save energy consumption.

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