The segregation and pile-up of arsenic atoms at the Si/SiO2 interface in steady state was investigated in detail by a combination of gracing incidence x-ray fluorescence spectroscopy (GI-XRF) measurements, electrical measurements, etching on the nanometer scale, and measurements of the step heights by interferometry. Using GI-XRF measurements and removal of the highly doped segregation layer by a sensitive etching process it was possible to distinguish clearly between the piled-up atoms and the arsenic atoms in the bulk over a large range of implantation doses, from 3×1012 to 1×1016 cm−2. The samples were annealed at different temperatures from 900 °C to 1200 °C for time periods long enough to make sure that the segregation reflects an equilibrium state. With additional step height measurements at line-space structures, the thickness of the layer with the piled-up arsenic and the shape of the segregation profile was determined. Electrical measurements indicated that the segregated arsenic atoms are deep donors with an electrical activity that increases eventually to full electrical activation for high sheet concentrations of the segregated atoms. The measured data can be modeled as a steady state of neutral arsenic atoms in the segregation layer with positively charged substitutional arsenic atoms and free electrons. For the highest concentration, a saturation of the sheet concentration of segregated arsenic atoms was observed that correlates with the increase in electrical activation. For the use in process simulation programs, a three-phase segregation model was adapted and calibrated.

A leading edge 45 nm CMOS system-on-chip (SOC) technology using Hafnium-based high-k/metal gate transistors has been optimized for low power products. PMOS/NMOS logic transistor drive currents of 0.86/1.08 mA/um, respectively, have been achieved at 1.1 V and off-state leakage of 1 nA/um. Record RF performance for a mainstream 45nm bulk CMOS technology has been achieved with measured f T /f MAX values of 395GHz/410GHz for NMOS and 300GHz/325GHz for PMOS with 28nm L gate transistors. HV I/O transistors with robust reliability and other SOC features, including linear resistors, MIS and MIM capacitors, varactors, inductors, vertical BJTs, precision diodes and high density OTP fuses are employed for HV I/O, analog and RF circuit integration.

The pile-up of arsenic at the Si/SiO(2) interface after As implantation and annealing was investigated by high resolution Z-contrast imaging, electron energy-loss spectroscopy (EELS), grazing incidence x-ray fluorescence spectroscopy (GI-XRF), secondary ion mass spectrometry, x-ray photoelectron spectroscopy, Rutherford backscattering spectrometry, as well as Hall mobility and four-point probe resistivity measurements. After properly taking into account their respective artifacts, the results of all methods are compatible with each other, with EELS and GI-XRF combined with etching providing similar spatial resolution on the nanometer scale for the dopant profile. The sheet concentration of the piled-up As at the interface was found to be similar to 1 x 10(15) cm(-2) for an implanted dose of I X 1016 cm-2 with a maximum concentration of similar to 10 at. %. The strain observed in the Z-contrast images also suggests a significant concentration of local distortions within 3 nm from the interface, which, however, do not seem to involve intrinsic point defects

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