Characterization of the pile-up of As at the SiO&lt;inf&gt;2&lt;/inf&gt;/Si interface

Steen, C.; Martinez-Limia, Alberto; Pichler, P.; Ryssel, H.; Pei, Lirong; Duscher, Gerd; Windl, Wolfgang

doi:10.1109/essderc.2007.4430929

Cited by 3 publications

(3 citation statements)

References 9 publications

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“…The scalability is further improved using lower energy (less-amorphizing) implants. Next to the poor re-crystallization in narrow fins due to the proximity of Si/SiO 2 interfaces, other phenomena such as dopant segregation at grain boundaries and interfaces (12) and poor dopant activation (13) and retention can contribute to a higher series resistance for the extension region in aggressively scaled fins. Non-amorphizing implants or other conformal doping techniques such as plasma doping (14) or vapor phase doping (15) could alleviate problematic re-crystallization in ultra-thin Si body.…”

Section: Fin Width Scalingmentioning

confidence: 99%

Material Aspects and Challenges for SOI FinFET Integration

et al. 2008

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FinFET is a promising device concept towards the 32 nm CMOS technology node and beyond as it combines the benefits of multigated architecture, intrinsically having superior scaling behavior, with a highly manufacturable process. The present paper will deal with material aspects of the SOI FinFET integration. We investigate scalability, performance and variability of high aspect ratio trigate FinFETs fabricated with 193nm immersion lithography and conventional dry etch. The effect of gate stack conformality on device performance is studied. The use of ion implantation for extension and the selective epitaxial growth of Si to achieve larger contact area on the source/drain areas are discussed from a materials perspective.

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Section: Fin Width Scalingmentioning

confidence: 99%

Material Aspects and Challenges for SOI FinFET Integration

et al. 2008

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“…We used a segregation model similar to that proposed by Lau et al where dopants can segregate to the Si/SiO interface from both silicon and oxide side, and we considered in addition deactivation of the segregated atoms at the interface. We calibrated the model with the results of segregation experiments reported by Steen et al [19], and were able to determine the concentration of trapping sites at the interface and the temperature dependence of emission and trappings rates [21].…”

Section: ( ) ( )mentioning

confidence: 99%

Modeling of the Diffusion and Activation of Arsenic in Silicon Including Clustering and Precipitation

Martinez-Limia

Pichler

Steen

et al. 2007

SSP

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We have developed a diffusion and activation model for implanted arsenic in silicon. The model includes the dynamic formation of arsenic-vacancy complexes (As4V) as well as the precipitation of a SiAs phase. The latter is mandatory to correctly describe concentrations above solid solubility while the former are needed to describe the reduced electrical activity as well as the generation of self-interstitials during deactivation. In addition, the activation state after solid-phase epitaxy and the segregation at the interface to SiO2 are taken into account. After implementation using the Alagator language in the latest version of the Sentaurus Process Simulator of Synopsys, the parameters of the model were optimized using reported series of diffusion coefficients for temperatures between 700 °C and 1200 °C, and using several SIMS profiles covering annealing processes from spike to very long times with temperatures between 700 °C and 1050 °C and a wide distribution of implantation energies and doses. The model was validated using data from flash-assisted RTP and spike annealing of ultra-low energy arsenic implants.

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“…In principle, an elastoplastic model would be necessary to properly estimate the stress field surrounding the silicon dot for low oxidation temperatures [35]. The third limitation is the modeling of the pile-up of arsenic at the Si/SiO 2 interface [36]. Despite these fundamental modeling restrictions, it will be shown that interesting trends can be extracted based on the relatively good description of experimental oxidation kinetics in the presence of arsenic by the coupling of the Ho and Plummer model [18], [19] and the Deal and Grove models [21].…”

Section: Bmentioning

confidence: 99%

Process Optimization and Downscaling of a Single-Electron Single Dot Memory

Krzeminski

Tang

Reckinger

et al. 2009

IEEE Trans. Nanotechnology

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This paper presents the process optimization of a single-electron nanoflash electron memory. Self-aligned single dot memory structures have been fabricated using a wet anisotropic oxidation of a silicon nanowire. One of the main issue was to clarify the process conditions for the dot formation. Based on the process modeling, the influence of various parameters (oxidation temperature, nanowire shape) has been investigated. The necessity of a sharp compromise between these different parameters to ensure the presence of the memory dot has been established. In order to propose an aggressive memory cell, the downscaling of the device has been carefully studied. Scaling rules show that the size of the original device could be reduced by a factor of 2. This point has been previously confirmed by the realization of single-electron memory devices.Index Terms-Device scaling, flash memories, nonvolatile memories, process modeling, quantum dot, scaling limits, silicon-oninsulator (SOI) technology, single-electron device.

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Characterization of the pile-up of As at the SiO<inf>2</inf>/Si interface

Cited by 3 publications

References 9 publications

Material Aspects and Challenges for SOI FinFET Integration

Material Aspects and Challenges for SOI FinFET Integration

Modeling of the Diffusion and Activation of Arsenic in Silicon Including Clustering and Precipitation

Process Optimization and Downscaling of a Single-Electron Single Dot Memory

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