No abstract

In this work, a ten-way power-combined power amplifier is designed using a load modulated balanced amplifier (LMBA)-based architecture. To provide the required magnitude and phase controls between the main and control-signal paths of the LMBA, an unequal power splitter and a phase compensation network are proposed. As proof of concept, the designed power amplifier is implemented in a 45-nm SOI CMOS process. At 40 GHz, it delivers a 25.1 dBm Psat with a peak power-added efficiency (PAE) of 27.9%. At 6-dB power back-off level, it achieves 1.39 times drain efficiency enhancement over an ideal Class-B power amplifier. Using a 200-MHz single-carrier 64-QAM signal, the designed amplifier delivers an average output power of 16.5 dBm with a PAE of 13.1% at an EVMrms of -23.9 dB and ACPR of -25.3 dBc. The die size, including all testing pads, is only 1.92 mm 2 . To the best of the authors' knowledge, compared with the other recently published silicon-based LMBAs, this design achieves the highest Psat.Index Terms -Doherty amplifier, load-modulated balanced amplifier (LMBA), millimeter-wave (mm-wave) power amplifier, power back-off capability, radio-frequency integrated circuits (RFIC), silicon-on-insulator (SOI).

No abstract

Power-handling capability of bulk CMOS-based single-pole double-throw switch operating in millimetre-wave and sub-THz region is significantly limited by the reduced threshold voltage of deeply scaled transistors. A unique design technique based on impedance transformation network is presented in this work, which improves 1-dB compression point, namely P1dB, without deteriorating other performance. To prove the presented solution is valid, a 70-100 GHz switch is designed and implemented in a 55-nm bulk CMOS technology. At 90 GHz, it achieves a measured P1dB of 15 dBm, an insertion loss of 3.5 dB and an isolation of 18 dB. The total area of the chip is only 0.14 mm 2 .