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As an error correction code, Low Density Parity Check (LDPC) code has been widely used in various communication standards such as WiMAX and DVB-S2. But these continuously-evolving communication standards and the high development cost and low-flexibility of hardwired ASIC solutions have pushed LDPC researchers to turn to more cost-efficient and flexible implementation, and thus the multi-core processor based implementation of LDPC decoder is gaining increasing attention in the last few years. However, the performance of the multi-core processor based implementation is far below the hardwired ASICs, with one of the key reasons that the cost of communication between processors is very high. Three approaches are proposed in this paper to reduce the communication cost, including: optimized algorithm partitioning to reduce communication traffic, utilizing imbalanced communication between tasks to optimize mapping and reduce overall communication distance, and simplified data sending-receiving mechanism to reduce the cost of identifying received data. By using these approaches, the communication time of the proposed implementation of LDPC decoder only accounts for 12.2% of total decoding time, which generally occupies 50% decoding time in the previously reported LDPC decoders on multi-core processors. And our work can achieve better throughput performance under the same hardware condition compared with other state-of-the-art works. I. INTRODUCTIONDuring the past decades hardwired ASICs are the most prevalent implementation of LDPC decoder, as it has the advantage of low area and high performance. However, facing the continuously-evolving communication standards, the drawbacks of ASIC design such as high development cost, poor time-to-market, short product life and low-flexibility are increasingly conspicuous. In regard to these shortages, programmable solutions based on multi-core processor were proposed, which have intrinsic flexibility, low cost and improved time-to-market and high parallel computational capability.Nevertheless, the implementation of LDPC decoder based on multi-core processor platform is a challenge topic as its performance is still far below ASICs. One restricting factor of the improvement of its performance is the inter-processors communication cost. For example, in [1] and [2], nearly 50% of the decoding time is actually spent on transferring data between processors.Reducing communication cost can be implemented in following aspects. The first is to reduce the communication traffic. In section 3, the quantitative analysis of the communication traffic under different orientations of algorithm partition is given and the horizontal partition is proved to have least communication traffic for most structures of LDPC codes. The second way is to reduce the overall communication distance. In section 4, this paper proposes the idea that utilizes the imbalance of communication between LDPC tasks to optimize the mapping and reduce the overall communication distance. Last, reducing the cost of identifying the ...

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