Dynamic and active pixel vision sensors (DAVISs) are a new type of sensor that combine a frame-based intensity readout with an event-based temporal contrast readout. This paper demonstrates that these sensors inherently perform highspeed, video compression in each pixel by describing the first decompression algorithm for this data. The algorithm performs an online optimization of the event decoding in real time. Example scenes were recorded by the 240x180 pixel sensor at sub-Hz frame rates and successfully decompressed yielding an equivalent frame rate of 2kHz. A quantitative analysis of the compression quality resulted in an average pixel error of 0.5DN intensity resolution for non-saturating stimuli. The system exhibits an adaptive compression ratio which depends on the activity in a scene; for stationary scenes it can go up to 1862. The low data rate and power consumption of the proposed video compression system make it suitable for distributed sensor networks.

Memristive devices represent a promising technology for building neuromorphic electronic systems. In addition to their compactness and non-volatility features, they are characterized by computationally relevant physical properties, such as state-dependence, non-linear conductance changes, and intrinsic variability in both their switching threshold and conductance values, that make them ideal devices for emulating the bio-physics of real synapses. In this paper we present a spiking neural network architecture that supports the use of memristive devices as synaptic elements, and propose mixed-signal analog-digital interfacing circuits which mitigate the effect of variability in their conductance values and exploit their variability in the switching threshold, for implementing stochastic learning. The effect of device variability is mitigated by using pairs of memristive devices configured in a complementary push-pull mechanism and interfaced to a current-mode normalizer circuit. The stochastic learning mechanism is obtained by mapping the desired change in synaptic weight into a corresponding switching probability that is derived from the intrinsic stochastic behavior of memristive devices. We demonstrate the features of the CMOS circuits and apply the architecture proposed to a standard neural network hand-written digit classification benchmark based on the MNIST data-set. We evaluate the performance of the approach proposed on this benchmark using behavioral-level spiking neural network simulation, showing both the effect of the reduction in conductance variability produced by the current-mode normalizer circuit, and the increase in performance as a function of the number of memristive devices used in each synapse.Neuromorphic computing systems comprise synapse and neuron circuits arranged in a massively parallel manner to support the emulation of large-scale spiking neural networks 1-9 . In many of these systems, and in particular in neuromorphic processing devices designed to overcome the von-Neumann bottleneck problem 7,8,10-14 , the bulk of the silicon real-estate is taken up by synaptic circuits that integrate in the same area both memory and computational primitives. To save area and maximize density in such devices, one possible approach is to implement very basic synapse circuits arranged in dense cross-bar arrays [15][16][17][18][19] . However, such approach is likely to relegate the role of the synapse to a basic multiplier 14,20 . In biology, synapses are extremely sophisticated structures that exhibit complex and powerful computational properties, including temporal dynamics, state-dependence, and stochastic learning behavior. The challenge is to design neuromorphic circuits that emulate these computational properties, and are also compact and low power. Memristive devices have recently emerged as nano-scale devices which provide a promising technology for addressing these problems 31,46 . These devices offer a compact and efficient solution to model synaptic weights since they are non-volatile, have ...