This study proposes a new approach for the optimization of phase and magnitude responses of fractional-order capacitive and inductive elements based on the mixed integer-order genetic algorithm (GA), over a bandwidth of four-decade, and operating up to 1 GHz with a low phase error of approximately ±1 • . It provides a phase optimization in the desired bandwidth with minimal branch number and avoids the use of negative component values, and any complex mathematical analysis. Standardized, IEC 60063 compliant commercially available passive component values are used; hence, no correction on passive elements is required. To the best knowledge of the authors, this approach is proposed for the first time in the literature. As validation, we present numerical simulations using MATLAB R and experimental measurement results, in particular, the Foster-II and Valsa structures with five branches for precise and/or high-frequency applications. Indeed, the results demonstrate excellent performance and significant improvements over the Oustaloup approximation, the Valsa recursive algorithm, and the continued fraction expansion and the adaptability of the GA-based design with five different types of distributed RC/RL network.
This paper deals with CMOS fractional-order inductance (FoL) simulator design and its utilization in 2.75 thorder Colpitts oscillator providing high frequency of oscillation. The proposed floating FoL is composed of two unity-gain current followers (CFs), two inverting voltage buffers, a transconductor, and a fractional-order capacitor (FoC) of order 0.75, while the input intrinsic resistance of CF is used as design parameter instead of passive resistor. The resulting equivalent inductance value of the FoL can be adjusted via order of FoC, which was emulated via 5 th-order Foster II RC network and values optimized using modified least squares quadratic method. In frequency range 138 kHz-2.45 MHz the L shows ±5 degree phase angle deviation. Theoretical results are verified by SPICE simulations using TSMC 0.18 μm level-7 LO EPI SCN018 CMOS process parameters with ±1 V supply voltages.
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