This paper presents a power-aware scheduling algorithm based on efficient distribution of the computing workload to the resources on heterogeneous CPU-GPU architectures. The scheduler manages the resources of several computing nodes with a view to reducing the peak power. The algorithm can be used in concert with adjustable power state software services in order to further reduce the computing cost during high demand periods. Although our study relies on GPU workloads, the approach can be extended to other heterogeneous computer architectures. The algorithm has been implemented in a real CPU-GPU heterogeneous system. Experiments prove that the approach presented reduces peak power by 10% compared to a system without any power-aware policy and by up to 24% with respect to the worst case scenario with an execution time increase in the range of 2%. This leads to a reduction in the system and service costs.

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Abstract-Image processing for intelligent cameras like those as the one presented in this paper is to provide very fast used in video surveillance applications implies computational and efficient dynamic reconfiguration, allowing the user to demanding algorithms activated in function of non predictable extensively exploit time multiplexing over a given set of silicon events, such as the content of the image or user requests. For extesi eoitetime m exin overagie setsofs such applications, hardwired acceleration must be restricted to resources. For intellgent cameras reconfigurable processors a minimum subset of kernels, due to the increasing NREs when provide an appealing alternative. They allow intensive runapplication update become necessary. Embedded reconfigurable time re-use of the acceleration logic, properly configurated to processors, coupling in the same computing engine a general-the specific (and possibly event-driven) required task. purpose embedded processor and field-programmable fabrics,In this paper, a motion detection algorithm requiring moreprovide an appealing trade-off point between pure software and dedicated hardware acceleration. As a case-study, this than 10 different basic operation kernelis rconsidered as a paper presents the implementation of a set of image processing case-study in order to show the possibilities offered by reconoperators utilized for motion detection on the DREAM adaptive figurable computing, and to analyze the different design trade-DSP. With respect to pure software solutions, the proposed imple-offs. A key point of this work is that impressive performance mentation achieves a performance improvement of 2-3 orders of improvements with respect to a software solution (2-3 order magnitude, while retaining the same degree of programmability ofmagnitude) were achieved after (roughly) 1 month of work and the same economical perspectives from the end-user point mostly performed by an unexperienced MSc student. Many commercial SoC solutions in the field of image in order to reduce data sizes while retaining most relevant processing or wireless telecommunication (e.g. ST Nomadik, informations. In many applications, the image processing flow TI OMAP, Philips Nexperia) feature today architectures based may depend on real-time events. As an example, motion detec-on a main control processor (commonly an ARM processor), tion could activate a procedure for object/human recognition. accelarated by a constellation of dedicated circuits or AppliTraditional implementation of this kind of image processing cation Specific DSPs. From an economical perspective, this algorithms consists in utilizing standard processors as control trend is very promising also for the incoming years, and in this engines and FPGAs as programmable accelerators. In fact, scenario we propose the DREAM adaptive DSP, developed in motion detection systems normally require average-low imple-the Morpheus project timeframe [2]. The DREAM [1] adaptive mentation costs, and such an approach is acceptable only for DSP is r...

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